{"id":2911457,"url":"https://alion.io/job/amd-verification-engineer","title":"Verification Engineer","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"A","score":95,"open_postings":8,"ghost_share":0,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":81,"computed_at":"2026-11-02T06:13:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":null,"work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Markham, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":72000,"max_usd":145000,"period":"year","method":"role_country_seniority_unknown","sample_n":164},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"Synopsys VC Formal","optional":true},{"name":"Synopsys VCS","optional":true}],"status":"live","first_seen_at":"2026-08-27T16:31:00Z","employer_posted_date":"2026-11-03","last_verified_at":"2026-11-03T02:41:05Z","board_verified":true,"closed_at":null,"days_open":67,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":67},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.\nWhether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.\n THE ROLE:\nThe verification team at AMD is looking for a Verification Engineer to lead and contribute on the verification of Network on Chip IPs and Subsystems. The individual will help architect, develop and use simulation and/or formal based verification environments, at block and subsystem level, to prove the functional correctness of Network-On-Chip (NOC) IPs, subsystems and SOC designs.\nTHE PERSON:\nYou are a skilled verification engineer with strong expertise in System Verilog and UVM, and a solid understanding of ASIC/SoC verification methodologies. You have experience verifying complex digital designs, ideally including NoC architectures, and are proficient in constraint-random, coverage-driven, and formal verification (SVA). You are analytical, detail-oriented, and collaborative, with the ability to debug complex issues, drive verification closure, and effectively partner with global design and architecture teams while taking ownership of challenging problems.\nKEY RESPONSIBILITIES:\nLead and Plan verification of complex digital design blocks by fully understanding the architecture and design specifications\nInteract with architects and design engineers to create a comprehensive verification test plan\nDesign and architect testbenches in System Verilog and UVM to complete verification of the design in an efficient manner\nCreate and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools\nDebug tests with design engineers to deliver functionally correct design blocks\nIdentify and write coverage measures for stimulus quality improvements\nPerform coverage analysis to identify verification holes and achieve closure on coverage metrics \nPREFERRED EXPERIENCE:\nExperienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level/full chip SOCs and FPGAs.\nStrong understanding of state of the art of verification techniques, including assertion and coverage-driven verification.\nStrong understanding of different phases of ASIC and/or full custom chip development is required.\nExperience in block level NOC (Net work on Chip) verification is a plus.\nVerification Experience in protocols like AXI3/4, DDR4/5, HBM, PCIe, Processors, Graphics is a plus.\nExperience as a verification architect, establishing the verification methodology, tools and infrastructure for high-performance FPGAs, SOCs and/or VLSI designs is a plus.\nExperience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus.\nFamiliarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus.\nExperience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (VC-Formal, Magellan) is a plus.\nACADEMIC CREDENTIALS:\nBachelors or Masters degree in computer engineering/Electrical Engineering \n#LI-HYBRID\n Benefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE:\nThe verification team at AMD is looking for a Verification Engineer to lead and contribute on the verification of Network on Chip IPs and Subsystems. The individual will help architect, develop and use simulation and/or formal based verification environments, at block and subsystem level, to prove the functional correctness of Network-On-Chip (NOC) IPs, subsystems and SOC designs.\nTHE PERSON:\nYou are a skilled verification engineer with strong expertise in System Verilog and UVM, and a solid understanding of ASIC/SoC verification methodologies. You have experience verifying complex digital designs, ideally including NoC architectures, and are proficient in constraint-random, coverage-driven, and formal verification (SVA). You are analytical, detail-oriented, and collaborative, with the ability to debug complex issues, drive verification closure, and effectively partner with global design and architecture teams while taking ownership of challenging problems.\nKEY RESPONSIBILITIES:\nLead and Plan verification of complex digital design blocks by fully understanding the architecture and design specifications\nInteract with architects and design engineers to create a comprehensive verification test plan\nDesign and architect testbenches in System Verilog and UVM to complete verification of the design in an efficient manner\nCreate and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools\nDebug tests with design engineers to deliver functionally correct design blocks\nIdentify and write coverage measures for stimulus quality improvements\nPerform coverage analysis to identify verification holes and achieve closure on coverage metrics \nPREFERRED EXPERIENCE:\nExperienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level/full chip SOCs and FPGAs.\nStrong understanding of state of the art of verification techniques, including assertion and coverage-driven verification.\nStrong understanding of different phases of ASIC and/or full custom chip development is required.\nExperience in block level NOC (Net work on Chip) verification is a plus.\nVerification Experience in protocols like AXI3/4, DDR4/5, HBM, PCIe, Processors, Graphics is a plus.\nExperience as a verification architect, establishing the verification methodology, tools and infrastructure for high-performance FPGAs, SOCs and/or VLSI designs is a plus.\nExperience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus.\nFamiliarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus.\nExperience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (VC-Formal, Magellan) is a plus.\nACADEMIC CREDENTIALS:\nBachelors or Masters degree in computer engineering/Electrical Engineering \n#LI-HYBRID\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","description_format":"text","description_chars":8672,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"Canada","iso":"CA","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-20T09:36:36Z"},{"event":"close","at":"2026-10-31T09:50:42Z"},{"event":"reopen","at":"2026-10-31T17:13:40Z"},{"event":"close","at":"2026-11-02T16:06:30Z"},{"event":"reopen","at":"2026-11-03T02:35:02Z"}],"visa":[],"liveness":{"score":58,"band":"ok","label":"Likely open","p_open":1,"p_active":0.779,"p_room":0.75,"age_days":66,"expected_fill_days":81,"reasons":["conf:1","velocity","win:late","comp:brand"],"computed_at":"2026-11-02T06:13:15Z"},"pay":null,"html_url":"https://alion.io/job/amd-verification-engineer","json_url":"https://alion.io/job/amd-verification-engineer.json","meta":{"generated_at":"2026-11-03T04:17:35Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":5824,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-04T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":93},"rest":"https://alion.io/mcp/rest/get_company?id=93"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Famd-verification-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Famd-verification-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Famd-verification-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/amd-verification-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Famd-verification-engineer"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":2911457}},{"tool":"search_jobs","arguments":{"company":"amd.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":2911457},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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