{"id":3878117,"url":"https://alion.io/job/ams-osram-senior-design-verification-engineer","title":"Senior Design Verification Engineer","company":{"id":54725,"name":"ams OSRAM","domain":"ams-osram.com","url":"https://alion.io/company/ams-osram","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SuccessFactors","truth_index":{"grade":"A","score":100,"open_postings":6,"ghost_share":0,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":16,"computed_at":"2026-11-09T06:03:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Plano, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-11-06T17:16:58Z","employer_posted_date":"2026-11-06","last_verified_at":"2026-11-09T13:29:31Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"We are seeking a highly motivated and experienced Senior Staff Design Verification Engineer to drive and collaborate on verification activities for complex semiconductor products. This is a senior individual contributor role focused on delivering high-quality verification solutions for advanced digital and mixed-signal integrated circuits.\nThe ideal candidate will be an expert in SystemVerilog and UVM-based verification methodologies, capable of independently driving verification planning, execution, coverage closure, and debug activities from specification through tapeout. The role offers the opportunity to grow into technical leadership through influence, expertise, and ownership of critical verification deliverables.\nKey Responsibilities: Verification Planning and Execution\nDevelop comprehensive Design Verification (DV) plans and verification strategies; define verification scope, coverage goals and signoff criteria\nIdentify and mitigate functional verification risks\nVerification Environment Development\nArchitect, implement, and maintain reusable UVM-based environments\nDevelop assertions, scoreboards, checkers, and coverage models\nDesign Verification\nPerform block-level, subsystem-level, and full-chip verification\nAnalyze architecture specifications and derive verification requirements\nDebug complex RTL, testbench, and integration issues\nCross-Functional Collaboration\nWork closely with Design, Architecture, AMS, Firmware, and Validation teams\nParticipate in design reviews and verification reviews; support customer technical discussions \nCommunicate verification status, risks, and closure metrics\nWho we are looking for\nEducation and Experience\nMaster's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with 8+ years of relevant industry experience (preferred)\nBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with 10+ years of relevant industry experience (minimum qualification)\nRequired Technical Skills\nExpert-level proficiency in SystemVerilog and UVM\nStrong knowledge of functional coverage development and coverage-driven verification\nStrong debug and root-cause analysis skills\nCreation of scoreboards, monitors, agents, predictors, and coverage models\nBlock-level, subsystem-level, and full-chip verification experience\nVerification planning and execution from specification through signoff\nStrong understanding of digital design fundamentals and ASIC/SoC architectures\nExperience reviewing RTL and identifying verification risks\nFamiliarity with scripting languages such as Python, Perl, or Tcl\nWhy Join Us\nYou will contribute to the verification of next-generation sensor and semiconductor products while working with a highly experienced engineering team. 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