{"id":950428,"url":"https://alion.io/job/analog-devices-senior-layout-engineer","title":"Senior Layout Engineer)","company":{"id":58431,"name":"Analog Devices","domain":"analog.com","url":"https://alion.io/company/analog-devices","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":78,"open_postings":81,"ghost_share":0,"stale_share":0.889,"repost_share":0,"time_to_fill_p50_days":42,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Limerick, Ireland"],"countries":["IE"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":78000,"max_usd":178000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":1655},"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Virtuoso","optional":false},{"name":"Keysight ADS","optional":false},{"name":"Perl","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-09-14T00:00:00Z","employer_posted_date":"2026-09-14","last_verified_at":"2026-10-17T02:18:48Z","board_verified":true,"closed_at":null,"days_open":34,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":34},"description":"About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\nSenior RF Layout Design Engineer\nAbout the Role\nThe RF Physical Design Engineer is responsible for the physical implementation, layout development, and verification of high-performance RF and mixed-signal integrated circuits. The engineer works closely with RFIC designers, process engineers, and product engineers to translate circuit schematics into manufacturable silicon while achieving performance, reliability, area, and yield objectives.This role requires a understanding of RF layout techniques, electromagnetic effects, process technologies, and physical verification methodologies to ensure first-pass silicon success.\nKey Responsibilities\nDevelop and implement physical layouts for RF, analog, mixed-signal, and passive circuit blocks.\nPerform floor planning and device placement to optimize RF performance, matching, isolation, and manufacturability.\nDesign high-frequency routing structures including transmission lines, transformers, inductors, baluns, and matching networks.\nCreate custom layouts for LNAs, mixers, PAs, VCOs, PLLs, switches, and other RF building blocks.\nVerification and Signoff\nPerform physical verification including: DRC (Design Rule Check)\n LVS (Layout Versus Schematic)\n ERC (Electrical Rule Check)\nAntenna and density checks\n\nSupport post-layout extraction and parasitic analysis.\nCollaborate with RF designers to resolve LVS, extracted performance, and yield-related issues.\nEnsure layouts meet process and foundry requirements.\nElectromagnetic Modelling\nGenerate and optimize layouts for RF passives.\nWork with RF designers to optimize EM simulation methodologies.\nTechnology and Methodology Development\nDevelop and maintain RF layout best practices.\nCreate reusable layout cells and design methodologies.\nLeverage AI advances in the RFIC layout flow.\nCross-Functional Collaboration\nPartner with RFIC designers from concept through tapeout.\nCollaborate with CAD, verification, process, and test engineering teams.\nParticipate in design reviews and tapeout readiness assessments.\nSupport silicon debug and failure analysis when required.\nRequired Qualifications\nEducation\nBachelor’s degree in electrical engineering, Electronics Engineering, Physics, or related field.\nExperience\nTypically, 3-5 years of experience in RFIC, analog, or mixed-signal physical design.\nExperience with advanced CMOS, SiGe BiCMOS, SOI, or RF CMOS technologies.\nIsolation structures\nCurrent density considerations\n\nFamiliarity with parasitic effects impacting RF performance.\nUnderstanding of high-frequency electromagnetic behaviour.\nEDA Tools\nExperience with one or more of:\nCadence Virtuoso Layout Suite\nKeysight ADS\nCadence EMX\nPreferred Qualifications\nExperience designing RF passives at frequencies from sub-GHz through mmWave.\nExperience supporting foundry tapeouts.\nFamiliarity with automotive, industrial, consumer, or wireless communication products.\nExperience with scripting languages such as SKILL, Python, Perl, or TCL.\nWhy You’ll Love Working at ADI\nAt Analog Devices, you'll be part of a collaborative and innovative team that's shaping the future of technology. We offer a supportive environment focused on professional growth, competitive compensation and benefits, work-life balance, and the opportunity to work on cutting-edge projects that make a real impact on the world.\nYou'll have access to continuous learning opportunities and mentorship from industry experts. Join us and help create the technologies that bridge the physical and digital worlds, making a tangible difference in how people live, work, and connect.\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position - except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) - may have to go through an export licensing review process.\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\nJob Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/Days","description_format":"text","description_chars":5196,"description_truncated":false,"requirements":{"experience_years_min":3,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Continuous learning"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Sensors & Transducers","Analog & Power Semiconductors"],"lifecycle":[{"event":"open","at":"2026-09-16T00:14:34Z"}],"visa":[],"liveness":{"score":42,"band":"fade","label":"Fading","p_open":1,"p_active":0.559,"p_room":0.75,"age_days":33,"expected_fill_days":42,"reasons":["conf:3","stale_co","velocity","win:late","comp:brand"],"computed_at":"2026-10-17T05:46:00Z"},"pay":null,"html_url":"https://alion.io/job/analog-devices-senior-layout-engineer","json_url":"https://alion.io/job/analog-devices-senior-layout-engineer.json","meta":{"generated_at":"2026-10-18T20:00:38Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":24040,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-19T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":58431},"rest":"https://alion.io/mcp/rest/get_company?id=58431"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fanalog-devices-senior-layout-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fanalog-devices-senior-layout-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fanalog-devices-senior-layout-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/analog-devices-senior-layout-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fanalog-devices-senior-layout-engineer"}]}