{"id":1395770,"url":"https://alion.io/job/analog-devices-senior-manager-design-verification-engineering","title":"Senior Manager, Design Verification Engineering","company":{"id":58431,"name":"Analog Devices","domain":"analog.com","url":"https://alion.io/company/analog-devices","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":77,"open_postings":77,"ghost_share":0,"stale_share":0.909,"repost_share":0,"time_to_fill_p50_days":42,"computed_at":"2026-10-14T06:34:16Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":18500,"max_usd":46000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":13},"experience_years_min":12,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Formal Verification","optional":false},{"name":"Python","optional":false},{"name":"SystemC","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-09-28T13:22:25Z","employer_posted_date":"2026-09-28","last_verified_at":"2026-10-14T20:26:45Z","board_verified":true,"closed_at":null,"days_open":16,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":16},"description":"About Analog Devices\nAnalog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.\nAnalog Devices is seeking Senior Manager, Design Verification Engineer, who will be responsible for design verification of highly integrated solutions and products in a multifunctional team. You will be working on driving real revenue growth on the next generation of Intelligence at the Edge products across multiple products and business units.\nAbout ADI:\nAnalog Devices, Inc. is a leading global high-performance analog technology company dedicated to solving our customers' most complex engineering challenges. We play a critical role at the intersection of the physical and digital world by providing the building blocks to sense, measure, interpret, connect, and power devices and systems. We design, manufacture, test, and market a broad portfolio of solutions, including integrated circuits (ICs), software and subsystems that leverage high-performance analog, mixed-signal and digital signal processing technologies. We embrace a culture of innovation and collaboration to push the state of the art.\nAbout the Role\nLead design verification team for SOC or subsystem design pre silicon verification. The candidate will be responsible for formulating verification strategies, Define verification architecture, Flow, Methodology and leading, driving and completing verification of large integrated products. As a senior team member, it is expected that he/she will lead and influence verification methodologies within both DBU and ADI. The candidate is also encouraged to participate in cross company technical initiatives as well as patent and publish work where possible.\nResponsibilities\nLead end-to-end SoC verification for complex digital SoCs, driving execution from planning to signoff.\nVerify complex microprocessor-based designs, AI/ML accelerators, and high-speed peripherals using advanced verification methodologies.\nDefine and drive team execution by planning tasks, tracking progress, and providing technical leadership, mentoring, and guidance.\nCollaborate closely with architecture and design teams to define requirements and align on verification deliverables and dependencies.\nDrive pre-silicon readiness by aligning with emulation, FPGA, and software teams to cover post-silicon validation scenarios early.\nDevelop and execute end-to-end system-level use cases for comprehensive functional validation.\nArchitect and implement scalable UVM-based testbenches, DV flows, and methodologies.\nDefine and review test plans; ensure closure of functional and code coverage across block, subsystem, and SoC levels.\nWork cross-functionally with emulation, FPGA, firmware, and system teams to ensure full-system correctness.\nApply formal verification techniques for IP and subsystem-level validation.\nLead NoC/interconnect verification and ensure robust data flow across the SoC.\nPerform performance verification and system-level analysis across real-world use cases.\nDrive innovation in verification strategies to meet aggressive schedules and quality goals.\nDefine overall verification strategy based on product requirements and design specifications, leveraging modern techniques such as formal, emulation, portable stimulus, and virtual platforms.\nRequirements\nB.Tech/M.Tech with 12+ years of experience in digital pre-silicon verification, including leadership across IP, subsystem, or SoC-level DV.\nStrong understanding of SoC/Subsystem architectures with hands-on expertise in Verilog/SystemVerilog and UVM-based testbench development, debugging, and methodology implementation.\nProven track record in verification closure using functional and code coverage metrics across block, subsystem, and SoC levels.\nExpertise in NoC, bus, and interconnect verification, along with coverage analysis and optimization.\nExperience in architecting scalable testbench environments and defining robust DV flows and methodologies.\nStrong background in power-aware verification (UPF), including power analysis and optimization.\nHands-on experience with formal verification, including flow definition, connectivity, and functional property checking.\nSolid protocol knowledge and verification experience across high-speed and low-speed interfaces such as I2C, SPI, Ethernet, UART, AXI/AHB, DMA, and SVI3.\nExperience in security and safety verification, ensuring compliance with secure design and functional safety requirements.\nFamiliarity with gate-level simulations with timing annotation (GLS).\nStrong expertise in test planning, constrained-random verification, assertions, and transaction-level modeling.\nGood understanding of processor-based systems (ARM, RISC-V, Tensilica), AI/ML accelerators, and proficiency in C/C++, SystemC, and scripting (Python/TCL/Shell).\nExposure to mixed-signal/analog verification (ADC/DAC/PLL/PHY) is a plus.\nExcellent communication and leadership skills with the ability to collaborate across global teams and drive verification innovation.\nStrong problem-solving mindset with the ability to quickly learn and adopt new technologies\nFor positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position - except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) - may have to go through an export licensing review process.\nAnalog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.\nJob Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/Days","description_format":"text","description_chars":6608,"description_truncated":false,"requirements":{"experience_years_min":12,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Sensors & Transducers","Analog & Power Semiconductors"],"lifecycle":[{"event":"open","at":"2026-09-28T13:22:25Z"}],"visa":[],"liveness":{"score":53,"band":"ok","label":"Likely open","p_open":1,"p_active":0.592,"p_room":0.9,"age_days":15,"expected_fill_days":42,"reasons":["conf:5","stale_co","velocity","win:mid","comp:brand"],"computed_at":"2026-10-14T06:34:16Z"},"pay":null,"html_url":"https://alion.io/job/analog-devices-senior-manager-design-verification-engineering","json_url":"https://alion.io/job/analog-devices-senior-manager-design-verification-engineering.json","meta":{"generated_at":"2026-10-14T20:45:56Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":27706,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-15T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":58431},"rest":"https://alion.io/mcp/rest/get_company?id=58431"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fanalog-devices-senior-manager-design-verification-engineering"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fanalog-devices-senior-manager-design-verification-engineering"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fanalog-devices-senior-manager-design-verification-engineering"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/analog-devices-senior-manager-design-verification-engineering\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fanalog-devices-senior-manager-design-verification-engineering"}]}