{"id":1266190,"url":"https://alion.io/job/anlagedigital-senior-design-verification-engineer","title":"Senior Design Verification Engineer","company":{"id":3800473,"name":"Anlage","domain":"anlagedigital.com","url":"https://alion.io/company/anlagedigital","size_band":null,"is_staffing_agency":true,"employer_type":"agency","is_intermediary":false,"listed_via":null,"ats_vendor":null,"truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India","Chennai, India","Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":17500,"max_usd":44000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":18},"experience_years_min":7,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence vManager","optional":false},{"name":"Cadence Xcelium","optional":false},{"name":"Formal Verification","optional":false},{"name":"Jenkins","optional":false},{"name":"MATLAB","optional":false},{"name":"Python","optional":false},{"name":"Synopsys Certitude","optional":false},{"name":"SystemC","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false}],"status":"live","first_seen_at":"2026-09-07T10:51:45Z","employer_posted_date":null,"last_verified_at":"2026-09-07T10:51:45Z","board_verified":false,"closed_at":null,"days_open":46,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":46},"description":"Design Verification (DV) Sr. Design Lead\n\nQualification : B.E / M.E / M.Tech or B.S / M.S in EE / CE\n\nExperience Level : 7 - 18 years\n\nJob Location : Bangalore, Chennai & Hyderabad\n\nSpecialization : PCIe SystemC IP / Subsystem Verification\n\nRole Objectives : \n\n- High quality silicon with no functional bugs by performing high quality pre-silicon verification\n\nKey Responsibilities : \n\n- Develop System Verilog compliant verification environments\n\n- Creation of verification plans and execution of coverage closure\n\n- Provide relevant reports to show progress\n\n- Run regressions / help set up automatic regressions\n\nSkillset : \n\n- Proven working experience within the semiconductor industry in constraint random functional and formal verification\n\n- Expertise in hardware verification using SystemVerilog/UVM\n\n- Preferably expertise in Specman E or willingness to learn on the job\n\n- Experience with mixed-signal IP with RNM/Verilog A model, Experience in C modelling for Digital Signal blocks\n\n- Experience in MATLAB modelling is an added advantage\n\n- Knowledge of using regression and coverage analysis tools, as well as knowledge of test bench qualification\n\n- Knowledge and experience with functional safety according to ISO26262\n\n- Working experience in international and cross-functional technical teams within a multi-cultural environment\n\n- Excellent English communication skills\n\nDeliverables : \n\n- Testcases ready for regression\n\n- Qualified verification environment using SystemVerilog and SpecMan e\n\n- Verification sign-off report fulfilling defined KPIs (e.g. 100% coverage)\n\n- Intermediate progress / KPI status reports on agreed frequency\n\n- Debug support to reach sign-off quality targets of IPs\n\n- Automation for regression runs (Jenkins) Certitude closure\n\nTools : \n\n- Xcelium, Vmanager Enterprise edition, System Verilog, VHDL, knowledge of scripting languages - perl / python, automation scripts with Jenkins\nSkills\nDesign Verification, PCI-e, SystemC, Verification, MATLAB, Mixed Signal, Verilog, System Verilog, IP Verification","description_format":"text","description_chars":2049,"description_truncated":false,"requirements":{"experience_years_min":7,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":[],"lifecycle":[{"event":"open","at":"2026-09-25T22:00:00Z"}],"visa":[],"liveness":{"score":7,"band":"cold","label":"Long shot","p_open":0.4,"p_active":0.407,"p_room":0.45,"age_days":45,"expected_fill_days":27,"reasons":["seen:45","agency","velocity","win:tail"],"computed_at":"2026-10-23T05:54:15Z"},"pay":null,"html_url":"https://alion.io/job/anlagedigital-senior-design-verification-engineer","json_url":"https://alion.io/job/anlagedigital-senior-design-verification-engineer.json","meta":{"generated_at":"2026-10-23T13:03:19Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":19391,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-24T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":3800473},"rest":"https://alion.io/mcp/rest/get_company?id=3800473"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fanlagedigital-senior-design-verification-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fanlagedigital-senior-design-verification-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fanlagedigital-senior-design-verification-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/anlagedigital-senior-design-verification-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fanlagedigital-senior-design-verification-engineer"}]}