{"id":3539291,"url":"https://alion.io/job/anthriq-lead-rtl-design-engineer","title":"Lead RTL Design Engineer","company":{"id":3795523,"name":"Anthriq","domain":"anthriq.com","url":"https://alion.io/company/anthriq","size_band":"11-50","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":null,"truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":28000,"max_usd":65000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":796},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Synopsys Design Compiler","optional":false},{"name":"Synopsys PrimeTime","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Formal Verification","optional":true},{"name":"Xilinx Vivado","optional":true}],"status":"live","first_seen_at":"2026-10-30T18:36:15Z","employer_posted_date":null,"last_verified_at":"2026-10-30T18:36:15Z","board_verified":false,"closed_at":null,"days_open":3,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":3},"description":"We need a strong RTL expert who can lead our silicon program to tapeout. You will be the technical bridge between our architecture and our design partner, owning every step from RTL freeze to GDSII handoff, and working with our partners. You will also build and lead the RTL team of 5-7 engineers. This is a hands-on lead role. You write RTL, review RTL, run synthesis, and own the result. The architect defines what gets built. You own how it gets built.\n\nResponsibilities: \nTranslate the architecture specification into synthesizable SystemVerilog.\nOwn the RTL coding standards, linting rules, and design methodology.\nLead a team of 5-7 RTL engineers through the full design cycle.\nOwn the synthesis flow (Design Compiler or Genus) and drive timing closure.\nDefine and maintain SDC timing constraints.\nReview all RTL code submissions for correctness, synthesizability, and style.\nCoordinate with the outsource partner on GDSII handover (netlist, constraints, floorplan guidance).\nWork closely with the verification team to resolve bugs and achieve coverage closure.\n\nRequirements: \n8+ years of RTL design experience in SystemVerilog.\nAt least 1 tapeout through to GDSII (not just RTL — you've seen the full flow).\nSynthesis and timing closure experience (Design Compiler or Genus, PrimeTime or Tempus).\nProcessor, DSP, or datapath-heavy design experience.\nFamiliarity with advanced process nodes (28nm class or below).\nStrong code review skills; you can spot timing hazards, FSM issues, and nonsynthesizable patterns in review.\nComfortable leading a small team while remaining hands-on.\n\nGood to have: \nVLIW or vector processor design experience.\nExperience with deterministic/real-time architectures (no caches, fixed latencies).\nFormal verification awareness (writing SVA, working with formal tools).\nSOC OR FPGA prototyping experience (Vivado).\n\nSoft Skills: \nStrong systems thinking with the ability to navigate large, complex FPGA architectures.\nExceptional problem-solving under tight timing and resource constraints.\nCross-functional collaboration with hardware, embedded software, DSP, and systems teams.\nExcellent communicator who documents clearly, presents confidently, and leads by example.\nAbility to make and defend architectural decisions under ambiguity and project pressure.\nSkills\nASIC, RTL, SOC","description_format":"text","description_chars":2315,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Health Care","Web Design","Neurotech & Neuromodulation"],"lifecycle":[{"event":"open","at":"2026-10-30T18:36:15Z"}],"visa":[],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":3,"expected_fill_days":27,"reasons":["seen:3","velocity","win:early"],"computed_at":"2026-11-03T05:54:40Z"},"pay":null,"html_url":"https://alion.io/job/anthriq-lead-rtl-design-engineer","json_url":"https://alion.io/job/anthriq-lead-rtl-design-engineer.json","meta":{"generated_at":"2026-11-03T06:38:41Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":9204,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-04T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":3795523},"rest":"https://alion.io/mcp/rest/get_company?id=3795523"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fanthriq-lead-rtl-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fanthriq-lead-rtl-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fanthriq-lead-rtl-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/anthriq-lead-rtl-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fanthriq-lead-rtl-design-engineer"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3539291}},{"tool":"search_jobs","arguments":{"company":"anthriq.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3539291},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}