Lead RTL Engineer

We are looking for a highly accomplished Lead RTL Engineer to drive our RTL development from architecture to tapeout while leading a high-performing engineering team. This is a hands-on technical leadership role where you will own the complete RTL implementation flow, working closely with architecture, verification, and physical design teams, as well as external design partners. You will be responsible for ensuring high-quality, synthesisable RTL and successful delivery through GDSII handoff.

Responsibilities:

• Translate architecture specifications into high-quality, synthesizable SystemVerilog RTL.
• Own RTL development methodology, coding standards, linting rules, and design best practices.
• Lead and mentor a team of 5-7 RTL design engineers throughout the complete ASIC design lifecycle.
• Drive RTL implementation from RTL freeze through synthesis and GDSII handoff.
• Own synthesis flow using Synopsys Design Compiler or Cadence Genus.
• Develop, maintain, and optimise SDC timing constraints to achieve timing closure.
• Perform comprehensive RTL code reviews to ensure functionality, synthesizability, coding quality, and timing efficiency.
• Identify and resolve RTL issues, including FSM design, timing hazards, and synthesis-related challenges.
• Collaborate closely with verification teams to resolve design issues and achieve functional and coverage closure.
• Coordinate with external ASIC implementation partners for netlist generation, timing constraints, floorplanning guidance, and successful GDSII delivery.
• Work cross-functionally with architecture, physical design, embedded software, DSP, and system engineering teams to ensure seamless execution.

Requirements:

• Bachelor's or master's degree in electronics, electrical engineering, computer engineering, or a related discipline.
• 7+ years of hands-on RTL design experience.
• Proven experience in SystemVerilog RTL development.
• Successfully completed at least one full ASIC tapeout through GDSII.
• Strong expertise in RTL synthesis and timing closure using Synopsys Design Compiler or Cadence Genus, PrimeTime or Cadence Tempus.
• Experience designing processor, DSP, or datapath-intensive architectures.
• Strong understanding of ASIC implementation flows and advanced semiconductor process technologies (28nm and below).
• Excellent RTL debugging and code review capabilities.
• Prior experience leading small engineering teams while remaining technically hands-on.

Skills

ASIC, Design Compiler, Genus, PrimeTime, RTL, SystemVerilog, Tempus, synthesis