{"id":3149794,"url":"https://alion.io/job/anthriq-lead-rtl-engineer","title":"Lead RTL Engineer","company":{"id":3795523,"name":"Anthriq","domain":"anthriq.com","url":"https://alion.io/company/anthriq","size_band":"11-50","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":null,"truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":28000,"max_usd":64000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":741},"experience_years_min":7,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Genus","optional":false},{"name":"Cadence Tempus","optional":false},{"name":"Synopsys Design Compiler","optional":false},{"name":"Synopsys PrimeTime","optional":false},{"name":"SystemVerilog","optional":false}],"status":"live","first_seen_at":"2026-10-23T11:35:15Z","employer_posted_date":null,"last_verified_at":"2026-10-23T11:35:15Z","board_verified":false,"closed_at":null,"days_open":0,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":0},"description":"We are looking for a highly accomplished Lead RTL Engineer to drive our RTL development from architecture to tapeout while leading a high-performing engineering team. This is a hands-on technical leadership role where you will own the complete RTL implementation flow, working closely with architecture, verification, and physical design teams, as well as external design partners. You will be responsible for ensuring high-quality, synthesisable RTL and successful delivery through GDSII handoff.\n\nResponsibilities: \nTranslate architecture specifications into high-quality, synthesizable SystemVerilog RTL.\nOwn RTL development methodology, coding standards, linting rules, and design best practices.\nLead and mentor a team of 5-7 RTL design engineers throughout the complete ASIC design lifecycle.\nDrive RTL implementation from RTL freeze through synthesis and GDSII handoff.\nOwn synthesis flow using Synopsys Design Compiler or Cadence Genus.\nDevelop, maintain, and optimise SDC timing constraints to achieve timing closure.\nPerform comprehensive RTL code reviews to ensure functionality, synthesizability, coding quality, and timing efficiency.\nIdentify and resolve RTL issues, including FSM design, timing hazards, and synthesis-related challenges.\nCollaborate closely with verification teams to resolve design issues and achieve functional and coverage closure.\nCoordinate with external ASIC implementation partners for netlist generation, timing constraints, floorplanning guidance, and successful GDSII delivery.\nWork cross-functionally with architecture, physical design, embedded software, DSP, and system engineering teams to ensure seamless execution.\n\nRequirements: \nBachelor's or master's degree in electronics, electrical engineering, computer engineering, or a related discipline.\n7+ years of hands-on RTL design experience.\nProven experience in SystemVerilog RTL development.\nSuccessfully completed at least one full ASIC tapeout through GDSII.\nStrong expertise in RTL synthesis and timing closure using Synopsys Design Compiler or Cadence Genus, PrimeTime or Cadence Tempus.\nExperience designing processor, DSP, or datapath-intensive architectures.\nStrong understanding of ASIC implementation flows and advanced semiconductor process technologies (28nm and below).\nExcellent RTL debugging and code review capabilities.\nPrior experience leading small engineering teams while remaining technically hands-on.\nSkills\nASIC, Design Compiler, Genus, PrimeTime, RTL, SystemVerilog, Tempus, synthesis","description_format":"text","description_chars":2508,"description_truncated":false,"requirements":{"experience_years_min":7,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Health Care","Web Design","Neurotech & Neuromodulation"],"lifecycle":[{"event":"open","at":"2026-10-23T11:35:15Z"}],"visa":[],"liveness":{"score":86,"band":"hot","label":"Hiring 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