{"id":3024528,"url":"https://alion.io/job/anthriq-sr-verification-engineer-rtl","title":"Sr. Verification Engineer (RTL)","company":{"id":3795523,"name":"Anthriq","domain":"anthriq.com","url":"https://alion.io/company/anthriq","size_band":"11-50","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":null,"truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":18000,"max_usd":48000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":18},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Formal Verification","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys Verdi","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-10-21T18:35:00Z","employer_posted_date":null,"last_verified_at":"2026-10-21T18:35:00Z","board_verified":false,"closed_at":null,"days_open":5,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":5},"description":"As a Senior RTL Verification Engineer, you will drive verification strategy and execution for complex RTL designs, working closely with architects, RTL designers, firmware, compiler, and software teams. You will own the process from specification and verification planning through coverage closure and silicon readiness, while helping build scalable verification methodologies for Anthriq's next-generation silicon platform.\n\nResponsibilities: \nOwn verification strategy, planning, execution, and sign-off for complex IPs and SoC subsystems.\nDevelop scalable and reusable SystemVerilog/UVM verification environments.\nDefine test plans, verification metrics, coverage goals, and closure strategies.\nDevelop constrained-random, directed, assertion-based, and corner-case tests.\nBuild functional coverage models and drive coverage closure.\nDevelop and maintain SystemVerilog Assertions (SVA) and contribute to formal verification.\nDebug complex RTL, simulation, and system-level failures and drive issues to closure.\nVerify high-performance datapaths, pipelines, vector processing units, memory systems, interconnects, and control logic.\nWork closely with architecture and RTL teams to identify design risks and corner cases early.\nDrive verification at block, subsystem, and SoC levels.\nImprove verification infrastructure, regression frameworks, automation, and methodologies.\nParticipate in design reviews, verification reviews, and silicon readiness/sign-off activities.\nMentor junior and mid-level verification engineers and contribute to building a strong verification culture.\n\nRequirements: \n8+ years of experience in ASIC/SoC/RTL verification.\nStrong hands-on expertise in SystemVerilog and UVM.\nStrong understanding of digital design, computer architecture, and RTL fundamentals.\nProven experience owning verification of complex IPs or SoC subsystems.\nStrong expertise in constrained-random verification, functional coverage, and coverage closure.\nStrong experience with SVA and assertion-based verification.\nExcellent RTL and simulation debugging skills.\nExperience with industry-standard tools such as VCS, Verdi, Questa, or equivalent.\nStrong programming/scripting skills in Python, Perl, C/C++, or Shell.\nSkills\nSV, SystemVerilog, UVM, verification","description_format":"text","description_chars":2259,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Health Care","Web Design","Neurotech & Neuromodulation"],"lifecycle":[{"event":"open","at":"2026-10-21T18:35:00Z"}],"visa":[],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":5,"expected_fill_days":30,"reasons":["seen:5","velocity","win:early"],"computed_at":"2026-10-27T05:46:45Z"},"pay":null,"html_url":"https://alion.io/job/anthriq-sr-verification-engineer-rtl","json_url":"https://alion.io/job/anthriq-sr-verification-engineer-rtl.json","meta":{"generated_at":"2026-10-27T14:23:31Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":2863,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-28T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":3795523},"rest":"https://alion.io/mcp/rest/get_company?id=3795523"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fanthriq-sr-verification-engineer-rtl"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fanthriq-sr-verification-engineer-rtl"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fanthriq-sr-verification-engineer-rtl"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/anthriq-sr-verification-engineer-rtl\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fanthriq-sr-verification-engineer-rtl"}]}