{"id":2135541,"url":"https://alion.io/job/apple-asic-design-and-integration-engineer-2","title":"ASIC Design and Integration Engineer","company":{"id":12,"name":"Apple","domain":"apple.com","url":"https://alion.io/company/apple","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Apple Jobs","truth_index":{"grade":"A","score":93,"open_postings":893,"ghost_share":0,"stale_share":0.075,"repost_share":0,"time_to_fill_p50_days":138,"computed_at":"2026-10-12T06:55:09Z"}},"role":"Hardware","role_family":"Hardware","seniority":"middle","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Beaverton, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":133000,"max_usd":260000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":543},"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"SystemVerilog","optional":false}],"status":"live","first_seen_at":"2026-04-10T00:25:38Z","employer_posted_date":"2026-10-12","last_verified_at":"2026-10-12T21:38:35Z","board_verified":true,"closed_at":null,"days_open":185,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":184},"description":"Apple’s Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer to join our dynamic group. In this role, you will develop custom SoCs that drive the performance and efficiency of Apple’s products. You will work on cutting-edge technologies and collaborate with cross-functional teams to deliver groundbreaking solutions.\nDescription\nDesign and Development: Design, implementation, and verification of complex ASICs. Develop RTL using SystemVerilog and perform synthesis.\nVerification: Engage with simulation-based and formal verification teams to ensure robust design validation.\nIntegration and Testing: Collaborate with hardware and software teams to integrate digital designs into complex SoCs.\nTiming and Power Analysis: Conduct timing analysis and power optimization to achieve PPA goals.\nDocumentation and Reporting: Create detailed micro-architecture and design documentation.\nMinimum Qualifications\nMinimum of BS + 3 years relevant industry experience\nPreferred Qualifications\nEducational Background: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.\nExperience: 3+ years of proven experience in ASIC design, including RTL design and verification. Hands-on experience with ASIC design tools and methodologies is essential.\nTechnical Skills: Proficiency in SystemVerilog, RTL design, synthesis, and timing analysis.\nProblem-Solving: Strong analytical and problem-solving skills.\nCollaboration: Excellent communication and teamwork skills, work effectively in cross-functional teams.\nAttention to Detail: Meticulous attention to detail and a commitment to delivering high-quality designs.\nExperience with high-speed I/O design and protocols. Knowledge of PCIe is a plus.\nFamiliarity with custom ASIC design and FPGA prototyping.\nHands on experience in all aspects of front-end chip development process (e.g., CDC/RDC, LINT, LEC, etc.).\nKnowledge of low-power design techniques and power optimization strategies.","description_format":"text","description_chars":2002,"description_truncated":false,"requirements":{"experience_years_min":3,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":true},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Operating Systems","Laptops","Smartwatches & Fitness Trackers","Tablets"],"lifecycle":[{"event":"open","at":"2026-10-09T01:35:03Z"},{"event":"close","at":"2026-10-09T01:39:59Z"},{"event":"reopen","at":"2026-10-09T06:23:17Z"},{"event":"close","at":"2026-10-11T12:23:15Z"},{"event":"reopen","at":"2026-10-11T19:23:20Z"},{"event":"close","at":"2026-10-11T23:11:48Z"},{"event":"reopen","at":"2026-10-12T21:38:35Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 6,350 · green card filings: 37","filings_12m":6350,"filings_prev_12m":6527,"green_card_filings_12m":37,"median_offered_wage_usd":177355,"route":null,"cap_exempt":false,"checked_at":"2026-10-03T21:08:04+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":1366}],"liveness":{"score":27,"band":"fade","label":"Fading","p_open":1,"p_active":0.609,"p_room":0.44,"age_days":185,"expected_fill_days":138,"reasons":["conf:1","win:tail","crowd:brand"],"computed_at":"2026-10-12T22:42:01Z"},"pay":null,"html_url":"https://alion.io/job/apple-asic-design-and-integration-engineer-2","json_url":"https://alion.io/job/apple-asic-design-and-integration-engineer-2.json","meta":{"generated_at":"2026-10-12T22:42:01Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":37116,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-13T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":12},"rest":"https://alion.io/mcp/rest/get_company?id=12"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fapple-asic-design-and-integration-engineer-2"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fapple-asic-design-and-integration-engineer-2"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fapple-asic-design-and-integration-engineer-2"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/apple-asic-design-and-integration-engineer-2\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fapple-asic-design-and-integration-engineer-2"}]}