{"id":2133285,"url":"https://alion.io/job/apple-asic-design-engineer-cache-controller","title":"ASIC Design Engineer - Cache Controller","company":{"id":12,"name":"Apple","domain":"apple.com","url":"https://alion.io/company/apple","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Apple Jobs","truth_index":{"grade":"A","score":94,"open_postings":607,"ghost_share":0.002,"stale_share":0.005,"repost_share":0.082,"time_to_fill_p50_days":149,"computed_at":"2026-11-14T05:58:10Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":177000,"max_usd":401000,"period":"year","method":"role_country_seniority_unknown","sample_n":3123},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[],"status":"live","first_seen_at":"2026-07-29T17:23:30Z","employer_posted_date":"2026-11-13","last_verified_at":"2026-11-14T16:56:27Z","board_verified":true,"closed_at":null,"days_open":108,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":108},"description":"Apple is building the world’s fastest highly parallel mobile processing systems. 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In this role, you will work on crafting special purpose cache and controller which is part and parcel of the SOC memory hierarchy.\nDescription\nDesign and develop hardware for cache subsystem in high performance system on a chip (SoC).\nDevelop cache micro-architecture based on architecture guidelines and model analysis.\nExplore architecture trade-offs in system performance, area, and power consumption.\nDevelop and debug register-transfer level (RTL) design of various sections in the cache subsystem.\nWork on front-end netlist and area/timing analysis of the cache subsystem.\nWork with physical design team on the timing closure of the cache subsystem.\nMinimum Qualifications\nIn-depth knowledge of memory subsystem\nAcademic experience with RTL/micro-architecture development\nGood understanding of PPA (performance/power/area) tradeoffs\nB.S. in a relevant field + 0 years of industry experience\nPreferred Qualifications\nCache design background including good understanding of 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