{"id":2339770,"url":"https://alion.io/job/apple-asic-design-engineer-neural-engine-dma-2","title":"ASIC Design Engineer — Neural Engine DMA","company":{"id":12,"name":"Apple","domain":"apple.com","url":"https://alion.io/company/apple","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Apple Jobs","truth_index":{"grade":"A","score":89,"open_postings":835,"ghost_share":0,"stale_share":0.218,"repost_share":0.006,"time_to_fill_p50_days":90,"computed_at":"2026-11-08T05:47:12Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Sunnyvale, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":250000,"max_usd":456000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":527},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Edge AI","optional":false},{"name":"Formal Verification","optional":false},{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"SystemVerilog","optional":true},{"name":"Verilog","optional":true}],"status":"live","first_seen_at":"2026-07-08T16:30:38Z","employer_posted_date":"2026-11-08","last_verified_at":"2026-11-08T23:54:18Z","board_verified":true,"closed_at":null,"days_open":123,"trust":{"level":"ok","repost_count":1,"flags":[],"days_open":122},"description":"Computational photography, live language translation, and countless other on-device AI\ncapabilities depend on moving enormous amounts of data between memory and compute at\nexactly the right time. As part of our Silicon Engineering Group, you will design the\nhigh-performance DMA engines responsible for moving model weights and activation tensors\nbetween the memory subsystem and the Apple Neural Engine.\nIn this role, you will take end-to-end ownership of complex DMA subsystem blocks, shape\ntechnical direction across the team, and mentor engineers earlier in their careers. The\nwork you drive ships in Apple products used by billions of people every day.\nDescription\nAs an ASIC Design Engineer on the ANE DMA Design team, you will drive the design\nof DMA subsystem blocks from microarchitecture specification through tapeout. ANE DMA's\nscale and complexity means grappling with:\ndecomposing tensor surfaces into efficient fetch sequences; maximizing throughput under\nreal-world memory system conditions; maintaining data consistency across concurrent\nstreams; multi-level arbitration and ordering correctness; sizing latency-tolerant\nbuffering structures; and security and state isolation.\nIn this front-end design role, your work will include:\n- Taking end-to-end ownership of DMA subsystems through the full cycle: microarchitecture\nspecification, RTL implementation, front-end signoff (synthesis, timing closure, area\nand power analysis, linting, LEC), and design verification closure.\n- Writing well-parameterized RTL structured for clean timing and low power, including\nassertions and cover points that encode design intent and ensure verification\ncompleteness.\n- Collaborating across design, architecture, and physical implementation teams to make\nsound architectural trade-offs and drive solutions that meet performance, power, and\narea targets.\n- Working closely with design verification and formal verification teams to ensure\nfunctional correctness: reviewing test plans, debugging failures, and confirming the\ndesign's intended behavior is fully exercised.\nMinimum Qualifications\nBachelors Degree plus 10 years of industry experience\nPreferred Qualifications\nExperience designing SoC front-end RTL in Verilog or SystemVerilog through multiple\ntapeouts, including synthesis, timing closure, area and power analysis, linting, and\nlogic equivalence checks.\nExperience collaborating across design verification, formal verification, architecture,\nand physical implementation teams to specify, implement, and debug complex RTL blocks.\nExperience designing DMA microarchitecture: address sequencing, flow control,\narbitration, or transaction ordering.\nExperience with on-chip bus protocols (AMBA AXI, AHB, APB) and on-chip interconnect\nfabrics.\nBackground in adjacent high-bandwidth domains: networking SoCs, image and video\nprocessing pipelines, multimedia IP, or AI/ML accelerators.\nA track record of writing precise, thorough micro-architectural specifications that\nserve as the authoritative reference for design, verification, and integration teams.\nFamiliarity with scripting languages (Python, Perl, Tcl) for design automation.","description_format":"text","description_chars":3141,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":true},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Operating Systems","Laptops","Smartwatches & Fitness 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