{"id":2131153,"url":"https://alion.io/job/apple-asic-design-engineering-lead-soc-ip-dma","title":"ASIC Design Engineering Lead - SoC IP DMA","company":{"id":12,"name":"Apple","domain":"apple.com","url":"https://alion.io/company/apple","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Apple Jobs","truth_index":{"grade":"A","score":95,"open_postings":497,"ghost_share":0,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":191,"computed_at":"2026-10-20T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Sunnyvale, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":246000,"max_usd":467000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":609},"experience_years_min":20,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false}],"status":"live","first_seen_at":"2026-10-05T22:48:41Z","employer_posted_date":"2026-10-09","last_verified_at":"2026-10-20T15:30:45Z","board_verified":true,"closed_at":null,"days_open":14,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":14},"description":"In this highly visible, hands-on role, you will lead a team of engineers at the center of Apple's SOC IP DMA design effort. Balancing equal parts people management and technical leadership, you will guide your team through the full front-end design cycle, including microarchitecture, RTL delivery, and debug. Your leadership will ensure silicon-ready quality while fostering a culture of teamwork and collaboration, continuous learning, and engineering excellence. Your work will have direct impact on products used by millions of people worldwide.\nDescription\nAs a hands-on ASIC Design Engineering Lead, you will split your time equally between leading your team and contributing directly as a technical contributor. You will:\n- Work closely with the platform architecture team to understand and refine architectural requirements\nLead your team to define and document the micro-architecture\n- Provide high-level technical guidance, drive micro-architectural decisions, review team members’ work and provide feedback, and ensure quality and across the team's design work\n- Actively drive the development of design infrastructure, automation, and strategic use of AI and other emerging tools\n- Be hands-on with the all activities of the team, e.g. micro-architecture, RTL design, verification strategy, debug, and infrastructure development\n- Scope features, generate effort, area, and power estimates, and create bottoms-up project schedules and resourcing plans.\n- Partner with architecture, IP integration, chip integration, design verification, and formal verification teams to align on plans, milestones, and deliverables\n- Track execution, surface and resolve risks early, and communicate clearly to management and stakeholders\n- Lead, mentor, and grow a team of engineers; actively invest in each person's technical and professional development\n- Build a team culture grounded in teamwork and collaboration, intellectual honesty, design/idea sharing, and a genuine growth mindset\n- Manage interpersonal dynamics thoughtfully and cultivate strong relationships within the team and with cross-functional teams\nMinimum Qualifications\nBS and a minimum of 20 years relevant industry experience\nPreferred Qualifications\n10+ years of hands-on experience in front-end ASIC design\nExperience in technical leadership: accountable for multi-person deliverables, setting technical direction, and interfacing effectively with management and cross-functional partners.\nExperience managing people on a team strongly desired\nOutstanding written and verbal communication skills and cross-functional collaboration instincts\nExcellent project planning and execution skills: bottom-up scheduling, effort, area, and power estimation, milestone planning and execution, and resource management\nSolid understanding of SoC architecture and high performance designs particularly for high speed networking, AI/ML compute, image and video processing, and/or memory subsystems\nUnderstanding of design concepts including arbitration, flow control, address translation, caching, bandwidth, pipelining, real time quality-of-service, and AMBA protocols, (AXI, APB, etc.).\nUnderstanding of low-power design techniques including clock gating, power gating, and logic depth; Understanding of timing optimization and high-frequency design\nTrack record of driving innovation through building tools, infrastructure, and automation, and strategic use of emerging technologies including AI.\nFormal verification experience a plus","description_format":"text","description_chars":3494,"description_truncated":false,"requirements":{"experience_years_min":20,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":["Continuous learning","Professional development"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Incident Response","Operating Systems","Smartwatches & Fitness Trackers","Tablets"],"lifecycle":[{"event":"open","at":"2026-10-09T01:01:56Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 6,350 · green card filings: 37","filings_12m":6350,"filings_prev_12m":6527,"green_card_filings_12m":37,"median_offered_wage_usd":177355,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":1366}],"liveness":{"score":99,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.993,"p_room":1,"age_days":14,"expected_fill_days":191,"reasons":["conf:2","urgency","velocity","win:early","comp:brand"],"computed_at":"2026-10-20T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/apple-asic-design-engineering-lead-soc-ip-dma","json_url":"https://alion.io/job/apple-asic-design-engineering-lead-soc-ip-dma.json","meta":{"generated_at":"2026-10-20T17:46:20Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":20363,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-21T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":12},"rest":"https://alion.io/mcp/rest/get_company?id=12"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fapple-asic-design-engineering-lead-soc-ip-dma"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fapple-asic-design-engineering-lead-soc-ip-dma"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fapple-asic-design-engineering-lead-soc-ip-dma"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/apple-asic-design-engineering-lead-soc-ip-dma\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fapple-asic-design-engineering-lead-soc-ip-dma"}]}