{"id":2130290,"url":"https://alion.io/job/apple-design-verification-engineer","title":"Design Verification Engineer","company":{"id":12,"name":"Apple","domain":"apple.com","url":"https://alion.io/company/apple","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Apple Jobs","truth_index":{"grade":"B","score":75,"open_postings":925,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":49,"computed_at":"2026-10-10T05:45:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Cupertino, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":180000,"max_usd":405000,"period":"year","method":"role_country_seniority_unknown","sample_n":2478},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-10-08T16:34:13Z","employer_posted_date":"2026-10-09","last_verified_at":"2026-10-11T19:23:20Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"Join an accomplished team at Apple developing custom integrated circuits for Apple’s existing and future product lines. As a member of our mixed signal ASIC team, you will be responsible for verifying complex digital IP’s. You will work with the system architects and digital designers, making block level specifications clear and precise. You will use the specifications to build verification plans to exercise the functional, performance, stress cases, and error conditions in your blocks. You will own the creation of the verification testbenches, using formal verification and UVM based simulation. Then you will build the testcases using System Verilog Assertions and constrained random UVM testcases to get complete functional and code coverage for your blocks.\nDescription\nYou will participate in code reviews of other blocks in the chips, offering proposals to more efficiently achieve our goal of bug free designs on the first tapeout. In addition to traditional digital circuit simulation, you will have the opportunity to learn and use other verification techniques such as formal verification, digital mixed signal verification, and analog mixed signal simulation using state-of-the-art tools.\nAlthough the team is small, we supply silicon to most of Apple’s industry leading hardware development teams. We have a close-knit, high performing team ready to ready to mentor engineers entering the mixed signal ASIC development field. Join us in building Apple’s next generation products. Do you want to be a part of building the “surprise and delight” in Apple’s future products?\nMinimum Qualifications\nMasters degree or higher in Electrical Engineering or Computer Science\nExtensive course work in digital design and computer architecture\nFoundation in object oriented programming techniques\nLab courses or work experience with System Verilog\nFamiliar with constrained random verification techniques\nFamiliarity with clock domain crossing design and verification techniques\nSome course work in analog circuit design\nPreferred Qualifications\nCollaborate in developing precise design specifications for digital control blocks\nUse design specifications to create block and chip level verification plans\nArchitect and create block level verification elements\nAssist in architecting chip and system level verification environments\nUse System Verilog and UVM to develop drivers, tests, reference models and checkers\nDebug test failures and work with designers to develop fixes\nUse functional and code coverage to track progress and gauge tapeout readiness","description_format":"text","description_chars":2560,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Operating Systems","Laptops","Smartwatches & Fitness Trackers","Tablets"],"lifecycle":[{"event":"open","at":"2026-10-09T00:54:32Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 6,350 · green card filings: 37","filings_12m":6350,"filings_prev_12m":6527,"green_card_filings_12m":37,"median_offered_wage_usd":177355,"route":null,"cap_exempt":false,"checked_at":"2026-10-03T21:08:04+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":1366}],"liveness":{"score":40,"band":"fade","label":"Fading","p_open":1,"p_active":0.459,"p_room":1,"age_days":1,"expected_fill_days":49,"reasons":["conf:2","stale_co","evergreen","wave","urgency","velocity","win:early","comp:brand"],"computed_at":"2026-10-10T05:45:15Z"},"pay":null,"html_url":"https://alion.io/job/apple-design-verification-engineer","json_url":"https://alion.io/job/apple-design-verification-engineer.json","meta":{"generated_at":"2026-10-11T22:13:00Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":11776,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-12T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":12},"rest":"https://alion.io/mcp/rest/get_company?id=12"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fapple-design-verification-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fapple-design-verification-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fapple-design-verification-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/apple-design-verification-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fapple-design-verification-engineer"}]}