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At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product. Do you love working on challenges that no one has solved yet? As a member of our dynamic group, you will have the unique and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple’s customers every single day.\nDescription\nOur Hardware Technology team is responsible for Apple’s breakthrough custom silicon and hardware technologies including battery, applications processors, storage controllers, sensors silicon, display silicon and other chipsets across Apple’s entire product line.\nAs part of our CAD and Methodology team in Apple’s world-class Silicon Engineering Group, you will be involved with the complete DFT and ATPG CAD solution for all design projects.\n- Develop and implement DFT and ATPG flow\n- Participate in development and implementation of DFT architecture with design team\n- Work with the DFT and Synthesis CAD team to verify DFT implementations\n- Support tool and infrastructure to generate structural test vectors , analyzing and improving coverage\n- Work with DFT designers on STA, physical, power and logical issues\n- Drive DFT and ATPG vendor engagements\nMinimum Qualifications\nBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, plus 10+ years of industry experience\nProficiency in Tcl, Perl, and Python scripting\nExperience with industry-standard DFT and logic synthesis tools\nFamiliarity with scan architecture and scan compression techniques\nFamiliarity with IEEE 1500 core wrapping\nFamiliarity with scan stitching and scan reordering\nExperience with DFT setup, rule checking (DRC), and debug\nPreferred Qualifications\nKnowledge about industrial standards and practices in DFT, including ATPG, JTAG, and MBIST\nKnowledge of Verilog and/or VHDL, and experience with simulators and waveform debugging tools preferred\nExperience in debugging Compressed ATPG patterns, MBIST, and JTAG/1500-related issues\nFamiliarity with synthesis tools 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