Gate-level SigEM/SEB/FIT CAD Engineer
Confirmed on the employer's own hiring board on Oct 19, 2026. First seen by Alion on Apr 15, 2026. Apple scores B on the Alion truth index.
Imagine what you could do here! At Apple, new ideas have a way of becoming phenomenal products very quickly. Do you want to bring passion and dedication to your job? There's no telling what you could accomplish at Apple. The people who work here have reinvented entire industries with Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices - we continue to strengthen our commitment to leave the world better than we found it!
As a key member of our best-in-class CAD Group, you will be part of building innovative designs. We will apply your hands-on experience in electromigration (EM), static error band (SEB), failure in time (FIT), self-heating effect (SHE), and thermal analysis to develop, define, and refine the methodologies and flows for gate-level as well as transistor-level designs. Major tasks will include IP / SOC signal EM analysis for clock and data nets, SOC FIT budget validation, power-grid EM verification, 3DIC and interposer thermal integrity, power switch and standard cell EM/SHE characterization, design abstract and reuse, sign-off, and ECO, and much more. Are you ready to join some of the world's leading engineers, and help us deliver the next generation of ground-breaking Apple products?