{"id":2992065,"url":"https://alion.io/job/apple-gpu-physical-design-engineer-statiming","title":"GPU Physical Design Engineer, STA/Timing","company":{"id":12,"name":"Apple","domain":"apple.com","url":"https://alion.io/company/apple","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Apple Jobs","truth_index":{"grade":"A","score":94,"open_postings":1125,"ghost_share":0.001,"stale_share":0.036,"repost_share":0.02,"time_to_fill_p50_days":148,"computed_at":"2026-11-12T10:38:37Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":186000,"max_usd":366000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":1340},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false}],"status":"live","first_seen_at":"2026-07-17T20:53:51Z","employer_posted_date":"2026-11-12","last_verified_at":"2026-11-12T10:02:01Z","board_verified":true,"closed_at":null,"days_open":117,"trust":{"level":"ok","repost_count":1,"flags":[],"days_open":117},"description":"Do you love creating elegant solutions to sophisticated challenges? As part of our Silicon Engineering group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processors! You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. In this job, you will be responsible for timing closure of highly complex GPU designs that go in every Apple product and will have amazing opportunities to set new standards for the next generation GPU designs. You will gain exposure to different aspects of product development, from concept to post silicon validation! You will collaborate with a variety of fields including Architecture, RTL, Synthesis, Clocking, DFT, Physical design and Post silicon engineering to ensure the best design practices are followed for a smooth timing convergence.\nDescription\nIn this role you will:\n- Lead different STA activities at the same time by working with functional collaborators.\n- Identify dependencies and roadblocks for different STA items very early on and ensure a smooth execution of timing closure.\n- Participate in analysis leading to the definition of next generation products.\n- Interact with RTL, architecture teams to understand physical design constraints related to timing and be the central point of contact to provide these to backend design flows.\n- Work with Synthesis and Physical Design teams to implement the best design optimized for power, performance and timing.\n- Setting up all DFT modes and making sure all test features are properly timed.\n- Assemble the top level design for STA ensuring accurate analysis by reviewing all the logs and reports.\n- Create and maintain scripts and automation to ensure high quality STA reports and work with other teams for timing closure.\n- Run ECO flows on the design and responsible for close timing.\n- Drive and support tapeout activities by running a full suite of signoff checks to ensure a high quality silicon for manufacture.\n- Work with CAD and Vendors to constantly improve the flow and bring in groundbreaking features to the analysis flows.\n- Work with post silicon teams and product engineering for silicon debug activities.\nMinimum Qualifications\nBachelors degree in Computer Science or Computer Engineering + 10 years relevant experience.\nExperience in STA and leading timing closure efforts.\nExperience with STA concepts such as cross-talk, OCV, noise, etc.\nExperience with scripting languages like TCL, Python, Perl, shell scripting etc.\nExperience working with EDA tools and exposure to their APIs.\nPreferred Qualifications\nMasters degree preferred.\nA good track record for driving timing closure experience.\nAble to constraint the design for different modes of timing closure by working with IP, RTL, DFT teams.\nAble to independently work with other functional teams and make the right decisions to help timing closure.\nExperience working with post silicon debug and timing correlation.\nAble to contribute for improving PPA of the product.\nExperience in setting up freq. targets for future generations, experience working with new process technology enablement.","description_format":"text","description_chars":3173,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":true},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Operating Systems","Laptops","Smartwatches & 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