{"id":2993417,"url":"https://alion.io/job/apple-phy-rtl-design-engineer-2","title":"PHY RTL Design Engineer","company":{"id":12,"name":"Apple","domain":"apple.com","url":"https://alion.io/company/apple","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Apple Jobs","truth_index":{"grade":"A","score":90,"open_postings":824,"ghost_share":0,"stale_share":0.214,"repost_share":0.006,"time_to_fill_p50_days":122,"computed_at":"2026-11-11T05:49:22Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Sunnyvale, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":180000,"max_usd":406000,"period":"year","method":"role_country_seniority_unknown","sample_n":2844},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"MATLAB","optional":false},{"name":"UVM","optional":true}],"status":"live","first_seen_at":"2026-04-27T19:11:14Z","employer_posted_date":"2026-11-11","last_verified_at":"2026-11-11T16:28:00Z","board_verified":true,"closed_at":null,"days_open":197,"trust":{"level":"ok","repost_count":1,"flags":[],"days_open":197},"description":"Come join Apple’s growing wireless silicon development team. Our wireless SOC organization is responsible for all aspects of wireless silicon development. With a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering.\nDescription\nDevelop signal processing intensive design for wireless communication SoCs, including:\nWriting specifications, other documents, and defining Microarchitecture based on MATLAB/C system model. Architecting area and power. Efficient low latency designs with scalabilities and flexibilities. Work with algorithm and software team to ensure performance and power efficiency. Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless protocols.\nMinimum Qualifications\nBachelors degree in related field.\nUnderstanding of DSP fundamentals.\nDigital Communications knowledge.\nProficiency in RTL Design.\nPreferred Qualifications\nFamiliarity with UVM DV environment and AI based efficiency improvement flows.\nStrong fixed-point knowledge and extensive experience with bit-true cycle-accurate verifications.\nUnderstanding of Decoders - Viterbi, LDPC, Polar.\nUnderstanding of Filter design, multi-radix implementation, and compromises.\nKnowledgeable in modern design techniques and energy-efficient/low power logic design, and power analysis.\nFamiliarity with power estimation (vector-less and vector-based), modeling, profiling, and post-silicon power correlation.\nSolid understanding of wireless standards, such as IEEE 802.11, 802.15, Bluetooth or 3GPP is a plus.\nBackground in computer architecture.\nBus fabric, especially APB/AHB/AXI.\nPower management with multiple power domains.\nAbility to work well in a team and be productive under ambitious schedules.\nShould exhibit excellent interpersonal skills and be self-motivated and well-organized.\nExperience with FPGA and/or emulation platform desired.\nExcellent communication skills - both written, and oral.","description_format":"text","description_chars":2369,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Operating Systems","Laptops","Smartwatches & Fitness Trackers","Tablets"],"lifecycle":[{"event":"open","at":"2026-10-21T10:28:12Z"},{"event":"close","at":"2026-10-21T16:58:38Z"},{"event":"reopen","at":"2026-11-11T11:26:07Z"}],"visa":[{"country":"US","licensed_sponsor":true,"adverts_offering_sponsorship_24m":0,"sanctioned_now":false,"evidence":"H-1B filings in 12 months: 6,350 · green card filings: 39","filings_12m":6350,"filings_prev_12m":6528,"green_card_filings_12m":39,"median_offered_wage_usd":177313,"route":null,"cap_exempt":false,"checked_at":"2026-11-11T07:38:50+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":1366}],"liveness":{"score":11,"band":"cold","label":"Long shot","p_open":1,"p_active":0.403,"p_room":0.28,"age_days":197,"expected_fill_days":83,"reasons":["conf:1","win:tail","crowd:brand"],"computed_at":"2026-11-11T17:55:19Z"},"pay":null,"html_url":"https://alion.io/job/apple-phy-rtl-design-engineer-2","json_url":"https://alion.io/job/apple-phy-rtl-design-engineer-2.json","meta":{"generated_at":"2026-11-11T17:55:19Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":34280,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-12T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.1,"usd":0.01,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":12},"rest":"https://alion.io/mcp/rest/get_company?id=12"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fapple-phy-rtl-design-engineer-2"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":2,"usd":0.2},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fapple-phy-rtl-design-engineer-2"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.1,"usd":0.01},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fapple-phy-rtl-design-engineer-2"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/apple-phy-rtl-design-engineer-2\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fapple-phy-rtl-design-engineer-2"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":2993417}},{"tool":"search_jobs","arguments":{"company":"apple.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":2993417},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}