{"id":3049482,"url":"https://alion.io/job/apple-pll-design-engineer-3","title":"PLL Design Engineer","company":{"id":12,"name":"Apple","domain":"apple.com","url":"https://alion.io/company/apple","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Apple Jobs","truth_index":{"grade":"A","score":91,"open_postings":911,"ghost_share":0.001,"stale_share":0.151,"repost_share":0.003,"time_to_fill_p50_days":99,"computed_at":"2026-10-27T05:46:45Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Cupertino, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":235000,"max_usd":432000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":563},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":true}],"status":"live","first_seen_at":"2026-10-21T21:50:32Z","employer_posted_date":"2026-10-22","last_verified_at":"2026-10-27T03:45:41Z","board_verified":true,"closed_at":null,"days_open":5,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":5},"description":"At Apple, our products are revolutionizing the way people live across the globe. Within our Analog-Mixed/Signal group, your role will be crucial in pushing the boundaries of what our technology can achieve. We are dedicated to crafting high-quality, innovative hard IPs that surpass the ordinary, adjusting to the escalating complexity of SOC/PHY designs and multiplying projects within tight production schedules. Our environment thrives on these challenges, fueled by a team of exceptional individuals passionate about continual learning and making a substantial impact. If you excel in dynamic settings, relish collaborative problem-solving, and seek to make a societal impact through your work, you might be the ideal candidate for our team. At Apple, you'll join a culture that encourages you to take ownership of your career, supported by colleagues committed to making a difference.\nDescription\nIn this role, you will leverage your expertise to develop cutting-edge frequency synthesizers for a variety of applications, including Compute, SoC, SerDes, and Cellular technologies. Your work will directly contribute to maintaining Apple’s leadership in innovation and market presence, setting new standards in the tech industry\nMinimum Qualifications\nBSEE with at least 10 years of relevant experience\nPreferred Qualifications\nTechnical Expertise: Demonstrated proficiency in PLL/FLL and frequency synthesis architecture and circuit design. This includes digital and analog approaches, DCO/VCO design both RO and LC, Fractional-N, SSC, Spur and Jitter cancellation techniques ..etc\nGood understanding of band gaps, bias circuits, op-amps, LDOs, feedback and compensation techniques.\nClocking Mastery: Deep understanding of clocking fundamentals, with a solid grasp of phase noise, jitter analysis, budgeting, and feedback loop dynamics.\nSimulation and Modeling: Skilled in developing System Verilog models, and performing behavioral simulations to explore new architectural performance and impact on loop dynamics. Ability to design/debug RTL is a plus.\nAttention to Detail: Exceptional focus on understanding the problems at hand and their systemic impacts, ensuring thoroughness in problem-solving.\nInnovation and Learning: A history of innovation and self-directed learning, with demonstrated leadership skills and a growth mindset.\nTeam Collaboration: Outstanding teamwork capabilities paired with strong productivity and scripting skills, ideally with experience in using industry-standard design tools.","description_format":"text","description_chars":2513,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Operating Systems","Laptops","Smartwatches & Fitness Trackers","Tablets"],"lifecycle":[{"event":"open","at":"2026-10-22T01:51:31Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 6,350 · green card filings: 37","filings_12m":6350,"filings_prev_12m":6527,"green_card_filings_12m":37,"median_offered_wage_usd":177355,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":1366}],"liveness":{"score":99,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.993,"p_room":1,"age_days":5,"expected_fill_days":99,"reasons":["conf:2","urgency","velocity","win:early","comp:brand"],"computed_at":"2026-10-27T05:46:45Z"},"pay":null,"html_url":"https://alion.io/job/apple-pll-design-engineer-3","json_url":"https://alion.io/job/apple-pll-design-engineer-3.json","meta":{"generated_at":"2026-10-27T07:45:30Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":8414,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-28T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":12},"rest":"https://alion.io/mcp/rest/get_company?id=12"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fapple-pll-design-engineer-3"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fapple-pll-design-engineer-3"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fapple-pll-design-engineer-3"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/apple-pll-design-engineer-3\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fapple-pll-design-engineer-3"}]}