{"id":2339643,"url":"https://alion.io/job/apple-soc-physical-design-engineer-2","title":"SoC Physical Design Engineer","company":{"id":12,"name":"Apple","domain":"apple.com","url":"https://alion.io/company/apple","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Apple Jobs","truth_index":{"grade":"A","score":93,"open_postings":893,"ghost_share":0,"stale_share":0.075,"repost_share":0,"time_to_fill_p50_days":138,"computed_at":"2026-10-12T06:55:09Z"}},"role":"Hardware","role_family":"Hardware","seniority":"middle","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Jerusalem, Israel"],"countries":["IL"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":119000,"max_usd":277000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":712},"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Verilog","optional":true}],"status":"live","first_seen_at":"2026-10-12T10:32:04Z","employer_posted_date":"2026-10-12","last_verified_at":"2026-10-12T21:38:35Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"As a member of our Physical Design group, you will take an integral part in bringing large scale SoCs to life, helping us deliver the next generation of Apple's ground-breaking products.\nYou will own the physical design cycle at the partition/IP/Chip levels, including netlist to GDS implementation and verification.\nAre you ready to join some of the world's leading engineers and work with state of the art design flows and process technology?\nIf you possess the knowledge and experience in any of the physical design domains and practices with track record of tape-outs in sub-micron technology, come join our group!\nDescription\nAs a member of our Physical Design team in this highly visible role, you will directly own implementation and verification of design partition(s) / IPs (netlist to delivery of our final GDS) for a highly complex SoC utilizing state of the art process technology.\n* Implementation - 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