{"id":2994158,"url":"https://alion.io/job/apple-soc-upf-methodology-engineer-5","title":"SoC UPF Methodology Engineer","company":{"id":12,"name":"Apple","domain":"apple.com","url":"https://alion.io/company/apple","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Apple Jobs","truth_index":{"grade":"A","score":90,"open_postings":824,"ghost_share":0,"stale_share":0.214,"repost_share":0.006,"time_to_fill_p50_days":122,"computed_at":"2026-11-11T05:49:22Z"}},"role":"Hardware","role_family":"Hardware","seniority":"middle","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Beaverton, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":136000,"max_usd":262000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":609},"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-04-10T14:09:01Z","employer_posted_date":"2026-11-11","last_verified_at":"2026-11-12T04:23:18Z","board_verified":true,"closed_at":null,"days_open":215,"trust":{"level":"ok","repost_count":1,"flags":[],"days_open":215},"description":"Are you passionate about crafting solutions to intricate challenges? Join the Low Power group\nat Silicon Technologies and contribute to the development of cutting-edge technology and\ncapabilities for low-power chip design. Your work will fuel Apple’s next-generation chips!\nYou’ll play a crucial role in exploring AI/ML to design the workflow for the next generation of\nUPF. Additionally, you’ll refine our existing UPF framework and ensure its seamless integration\nand rigorous verification across our mobile products.\nYou will be part of an exciting silicon design group that is responsible for designing state-of-the-art ASICs.\nWe have an extraordinary opportunity for Power UPF Engineers, who will drive transistor level power ERC sign-off and power intent-UPF implementation & verification on mobile SOCs.\nDescription\nIn this role, your main objective will be to enhance our Unified Power Format (UPF)\nmethodologies, refining power intent specification, execution, and validation to support state-\nof-the-art mobile SOCs. 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