{"id":447422,"url":"https://alion.io/job/arago-senior-mixed-signal-verification-engineer","title":"Mixed-signal Verification Engineer","company":{"id":173018,"name":"Arago","domain":"arago.inc","url":"https://alion.io/company/arago-2","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Ashby","truth_index":{"grade":"B","score":83,"open_postings":4,"ghost_share":0,"stale_share":0.5,"repost_share":0,"time_to_fill_p50_days":76,"computed_at":"2026-10-27T05:46:45Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Paris, France","Tel Aviv, Israel"],"countries":["FR","IL"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":47000,"max_usd":90000,"period":"year","method":"role_country_seniority_unknown","sample_n":66},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":true}],"status":"live","first_seen_at":"2026-09-02T13:04:56Z","employer_posted_date":"2026-09-02","last_verified_at":"2026-10-27T13:06:13Z","board_verified":true,"closed_at":null,"days_open":55,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":55},"description":"Meet Arago and the Aragonians\nArago’s mission is to re-engineer the foundations of computing from first principles.\nThe explosive growth of AI is pushing the industry to rethink how processors are built. Arago is meeting that challenge with a proprietary technology that fuses optical and CMOS technologies to deliver an order-of-magnitude increase in performance.\nArago is the fastest, and currently the only, company to have built such a processor. It's backed by leading deep-tech investors and some of the most respected figures in semiconductors and computing, including the CEO of Arm, the founder of macOS who worked directly with Steve Jobs at Apple, an Nvidia Fellow, the Head of Optics at Google, and many other industry leaders.\nOur work is guided by three clear values: do great things, move with high velocity, and operate as one unit. We work in a demanding environment where constant learning, ownership, and execution are expected, and where exceptional people have the opportunity to do their life’s work.\nWhat you’ll do\nAs Mixed-Signal Verification Engineer you will own the methodology, planning, and execution of mixed-signal verification for digital-to-analog interfaces on Arago's Systems-on-Chip, working across analog, RTL, architecture, and firmware teams to ensure correct integration and drive verification to sign-off.\nRequired Skills and Experience\nStrong hands-on experience in ASIC or SoC verification.\n\nExperience verifying mixed-signal blocks or digital-to-analog and analog-to-digital interfaces.\n\nExperience with AMS (analog-mixed-signal) co-simulation flow, and setting up mixed-signal testbenches.\n\nStrong SystemVerilog skills and practical experience with UVM or an equivalent verification methodology.\n\nExperience building verification environments and developing tests, assertions, scoreboards, and functional coverage.\n\nGood understanding of both digital design fundamentals and basic analog/mixed-signal concepts.\n\nStrong debugging skills, including the ability to investigate issues spanning RTL, models, clocks, resets, configuration, and analog behavior.\n\nExperience with scripting and automation, preferably Python, Tcl, shell, or similar.\n\nLanguage: English at a proficient level.\n\nResponsibilities\nOwn the mixed-signal verification methodology and verification plan for digital-to-analog interfaces on Arago SoCs.\n\nBuild and maintain verification environments at block, subsystem, and SoC level.\n\nDevelop tests, assertions, checkers, scoreboards, and functional coverage.\n\nVerify digital control and configuration of analog/mixed-signal circuitry across normal operation, corner cases, and error conditions.\n\nRun regressions, analyze coverage, debug failures, and drive verification to sign-off.\n\nDevelop or integrate behavioral and real-number models needed for efficient mixed-signal simulation.\n\nWork closely with analog, RTL, architecture, firmware, and SoC verification teams to identify and resolve interface issues.\n\nNice to have\nVerification experience with complex high-speed interface IP such as PCIe, DDR/LPDDR, UCIe, SerDes, USB, CXL, or similar PHY-based interfaces.\n\nExperience verifying interface initialization, link training, calibration, adaptation, clocking, power-state transitions, or other digital/analog control loops.\n\nExperience with real-number modeling, SystemVerilog RNM, wreal, Verilog-AMS, or equivalent mixed-signal verification techniques.\n\nExperience developing or integrating behavioral models of analog/PHY components into digital verification environments.\n\nExperience with SoC-level integration and verification of complex interface IP.\n\nExperience with low-power verification, power-state management, or UPF.\n\nExperience driving a complex IP or SoC verification effort through coverage closure and tape-out.\n\nPay and benefits\nCompetitive cash compensation, with final package based on location, experience, and the pay of team members in similar positions.\n\nMeaningful stock option plan offered (included in the majority of full time offers).\n\nHealthcare coverage (including family-friendly options), pension contributions, professional development support, and 25 days of PTO, in addition to public holidays.\n\nOwnership of a key technical domain, with significant vertical and/or horizontal growth opportunities, based on performance and individual drive.\n\nWe look forward to hearing how you can help shape the future of AI at Arago.","description_format":"text","description_chars":4420,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[{"language":"English","level":"All levels","optional":false}]},"benefits":["Growth opportunities","Professional development"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-09-06T07:59:09Z"}],"visa":[],"liveness":{"score":56,"band":"ok","label":"Likely open","p_open":1,"p_active":0.749,"p_room":0.75,"age_days":54,"expected_fill_days":76,"reasons":["conf:1","win:late"],"computed_at":"2026-10-27T05:46:45Z"},"pay":null,"html_url":"https://alion.io/job/arago-senior-mixed-signal-verification-engineer","json_url":"https://alion.io/job/arago-senior-mixed-signal-verification-engineer.json","meta":{"generated_at":"2026-10-27T13:38:04Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":1878,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-28T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":173018},"rest":"https://alion.io/mcp/rest/get_company?id=173018"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Farago-senior-mixed-signal-verification-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Farago-senior-mixed-signal-verification-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Farago-senior-mixed-signal-verification-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/arago-senior-mixed-signal-verification-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Farago-senior-mixed-signal-verification-engineer"}]}