{"id":3488308,"url":"https://alion.io/job/arm-holdings-design-verification-engineer-memory-controller-ip","title":"Design Verification Engineer - Memory Controller IP","company":{"id":268,"name":"Arm Holdings","domain":"arm.com","url":"https://alion.io/company/arm","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Radancy","truth_index":{"grade":"A","score":85,"open_postings":54,"ghost_share":0,"stale_share":0.593,"repost_share":0,"time_to_fill_p50_days":45,"computed_at":"2026-11-03T05:54:40Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":null,"work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":113000,"max_usd":256000,"period":"year","method":"role_country_seniority_unknown","sample_n":3123},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Synopsys VCS","optional":true}],"status":"live","first_seen_at":"2026-10-29T22:27:04Z","employer_posted_date":"2026-10-29","last_verified_at":"2026-11-03T20:06:02Z","board_verified":true,"closed_at":null,"days_open":4,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":4},"description":"Job Overview\nJoin the Memory Controller IP verification team as a Design Verification Engineer and help deliver reliable IP for next-generation memory technologies. You will develop verification strategies and SystemVerilog/UVM environments to validate functionality, performance, and protocol behaviour across supported memory technologies. Collaborating with RTL designers, architects, and verification colleagues, you will investigate complex issues, support verification closure for assigned features, and contribute to the delivery of high-quality IP.\nResponsibilities\nDevelop and maintain SystemVerilog/UVM verification environments for Memory Controller IP.\nCreate verification plans, test scenarios, assertions, functional coverage models, and scoreboards from architectural specifications.\nDevelop constrained-random and directed tests to verify memory controller functionality across supported LPDDR and DDR technologies.\nAnalyse regressions, coverage, simulation waveforms, and logs to identify and resolve RTL, testbench, and protocol issues.\nPartner with RTL designers, architects, and verification teams to clarify behaviour, resolve issues, and support verification sign-off.\nImprove verification efficiency through scripting, automation, and verification methodology improvements.\nTake ownership of assigned features and deliver verification milestones to agreed schedules.\nRequired Skills and Experience\nPractical experience verifying ASIC or SoC designs using SystemVerilog and UVM, including constrained-random testing, assertions, scoreboards, and functional coverage.\nAbility to develop verification plans and translate architectural specifications into tests, coverage, and verification environments.\nUnderstanding of memory controller architecture and memory protocol concepts, including LPDDR or DDR technologies.\nAbility to debug RTL, testbench, and protocol issues using simulation tools, waveforms, and logs, and communicate findings clearly with cross-functional teams.\nNice-to-Have Skills and Experience\nExperience with LPDDR5, LPDDR6, DDR5, DDR6, or other memory technologies.\nKnowledge of DFI interfaces, including DFI 4.x or 5.x.\nFamiliarity with AMBA protocols such as AXI, ACE, or CHI.\nExperience with simulation and debug tools such as Synopsys VCS or Siemens Questa.\nExperience improving verification workflows through scripting, automation, or methodology development.\nIn Return\nThis role offers the opportunity to work on Memory Controller IP that supports evolving memory technologies and complex SoC designs. You will collaborate with specialists across RTL design, architecture, and verification while building deeper expertise in verification strategy, protocol analysis, coverage closure, and debugging. Your work will have a direct impact on the quality and readiness of assigned IP features and on how the team improves its verification approach.\nAdditional Information\nPlease note that no relocation package is available for this role.\nSalary Range:\n$249,900-$338,100 per yearWe value people as individuals and our dedication is to reward people competitively and equitably for the work they do and the skills and experience they bring to Arm. Salary is only one component of Arm's offering. The total reward package will be shared with candidates during the recruitment and selection process.\nOur 10x Mindset\nAt Arm, we believe progress happens when people are empowered to think bigger and push beyond what seems possible. Our 10x mindset is about curiosity, ambition and creating impact that will be used by millions. We learn fast, prioritise collaboration and turn bold ideas into real technology. We look for people who are inspired by this way of working and want to grow in an environment where bold ideas are welcomed. Discover how the 10x mindset shapes life at Arm: https://careers.arm.com/10x-mindset\nUse of AI in Your Application\nAt Arm, we embrace the benefits AI can bring, including in recruitment. You may use AI to support your preparation, such as improving the clarity of written responses, practicing interview questions, or learning more about our industry. However, your application and interview responses must reflect your own thinking, experience, and abilities. We want to understand your authentic perspective, creativity, and approach to problem solving. As such, you may not use AI to complete assigned tasks as part of any assessments. If you plan to use AI-supported or assistive technologies as part of a reasonable adjustment, please contact  so we can support you.\nRecruitment Adjustments and Accommodations\nAt Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.\nHybrid Working\nArm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.\nEqual Opportunities\nArm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.","description_format":"text","description_chars":6514,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":["Hybrid work"],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-10-29T22:27:04Z"}],"visa":[],"liveness":{"score":63,"band":"ok","label":"Likely open","p_open":1,"p_active":0.632,"p_room":1,"age_days":4,"expected_fill_days":45,"reasons":["conf:0","stale_co","velocity","win:early","comp:brand"],"computed_at":"2026-11-03T05:54:40Z"},"pay":null,"html_url":"https://alion.io/job/arm-holdings-design-verification-engineer-memory-controller-ip","json_url":"https://alion.io/job/arm-holdings-design-verification-engineer-memory-controller-ip.json","meta":{"generated_at":"2026-11-03T22:03:53Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":430,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-04T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":268},"rest":"https://alion.io/mcp/rest/get_company?id=268"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Farm-holdings-design-verification-engineer-memory-controller-ip"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Farm-holdings-design-verification-engineer-memory-controller-ip"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Farm-holdings-design-verification-engineer-memory-controller-ip"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/arm-holdings-design-verification-engineer-memory-controller-ip\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Farm-holdings-design-verification-engineer-memory-controller-ip"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3488308}},{"tool":"search_jobs","arguments":{"company":"arm.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3488308},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}