{"id":2031417,"url":"https://alion.io/job/asml-fpga-design-engineer","title":"FPGA Design Engineer","company":{"id":17151,"name":"ASML","domain":"asml.com","url":"https://alion.io/company/asml","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"middle","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Veldhoven, Netherlands"],"countries":["NL"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":54000,"max_usd":127000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":640},"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Git","optional":false},{"name":"Linux","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false}],"status":"live","first_seen_at":"2026-10-07T14:26:18Z","employer_posted_date":"2026-10-07","last_verified_at":"2026-10-08T21:53:28Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"Introduction to the job\nAs an FPGA Design Engineer, you will specify and design FPGA RTL blocks (IP) for data handling and synchronization in a complex communication network. These blocks are primarily developed in SystemVerilog and combined with other RTL blocks to create a complete FPGA system.\nYou will work in a multidisciplinary engineering team alongside FPGA designers, FPGA verification engineers, software developers, hardware engineers and system architects. Your work will span RTL design, requirements definition, stakeholder management, RTL design documentation, team alignment, debugging and hardware validation.\nRole and responsibilities\nAs an FPGA Design Engineer, you will translate requirements into reliable and maintainable FPGA RTL (IP) blocks. You will make design choices that affect development effort, performance, resource utilization, cost of goods, complexity and long-term maintainability.\nYou will:\nDesign RTL blocks in SystemVerilog, including robust exception handling for reset behavior, incomplete transfers and notifications to higher-level software, while preventing clock-domain crossing issues.\nDefine, document and negotiate requirements, including rationale, feasibility and verifiability.\nAnalyze design alternatives, perform trade-off studies and align implementation decisions with stakeholders.\nDocument RTL architecture, behavior and design decisions, and identify interface inconsistencies early.\nCollaborate with verification engineers, FPGA designers, software developers and integrators on block and system-level issues.\nDevelop and execute hardware tests for requirements not covered by simulation-based verification.\nCreate effort estimates with incomplete information and adapt to changing requirements.\nContribute to technical roadmaps, FPGA development practices, product integration and technical issue resolution.\nEducation and experience\nYou have a bachelor's or master's degree in electrical engineering, computer engineering or a related technical field.\nWe are looking for candidates with:\nThree or more years of experience in FPGA or digital RTL design.\nStrong hands-on experience designing synthesizable RTL in SystemVerilog, including the use of SystemVerilog interfaces.\nExperience developing FPGA RTL designs from requirements and architecture through implementation and integration.\nA good understanding of synchronous digital design, including clocking, resets, FPGA primitives, timing and finite-state machine design.\nExperience with FPGA simulation, linting, clock-domain crossing analysis, synthesis, implementation and timing analysis toolchains.\nExperience with digital communication, synchronization, networking or comparable data-processing applications.\nExperience with Linux, Git, Python and C.\nExperience working in multidisciplinary engineering environments.\nStrong written and verbal communication skills in English.\nExperience with high-speed digital interfaces or with developing reusable FPGA RTL is considered an advantage.\nSkills\nYou enjoy solving complex digital design problems and are comfortable working across the boundary between architecture and implementation.\nTo thrive in this role, you will need:\nStrong analytical and problem-solving skills.\nThe ability to translate complex requirements into clear, practical and maintainable RTL designs.\nA structured approach to digital design and technical problem-solving.\nThe ability to reason about architectural and implementation trade-offs.\nStrong collaboration skills across hardware, software and system disciplines.\nThe ability to prioritize tasks and work independently.\nClear technical communication and documentation skills.\nA proactive approach to improving designs, methods and engineering practices.\nOther information\nYou will join a multidisciplinary engineering team developing FPGA-based technology for complex, high-performance systems. The team develops reusable RTL blocks and works closely with hardware, software and system engineering teams from early architecture through product integration.\nThis position requires access to controlled technology, as defined in the United States Export Administration Regulations (15 C.F.R. § 730, et seq.). Qualified candidates must be legally authorized to access such controlled technology prior to beginning work. Business demands may require ASML to proceed with candidates who are immediately eligible to access controlled technology.\nInclusion and diversity\nASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, color, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity. We recognize that inclusion and diversity is a driving force in the success of our company.\nNeed to know more about applying for a job at ASML? Read our frequently asked questions.","description_format":"text","description_chars":4985,"description_truncated":false,"requirements":{"experience_years_min":3,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[{"language":"English","level":"All levels","optional":false}]},"benefits":[],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Manufacturing","Electronics Manufacturing","Semiconductor Manufacturing"],"lifecycle":[{"event":"open","at":"2026-10-07T14:26:18Z"}],"visa":[],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":0,"expected_fill_days":25,"reasons":["conf:1","velocity","win:early","comp:brand"],"computed_at":"2026-10-08T05:49:30Z"},"pay":null,"html_url":"https://alion.io/job/asml-fpga-design-engineer","json_url":"https://alion.io/job/asml-fpga-design-engineer.json","meta":{"generated_at":"2026-10-09T00:38:52Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":912,"day_limit":5000,"remaining_today":4088,"minute_limit":60,"resets_at":"2026-10-10T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":17151},"rest":"https://alion.io/mcp/rest/get_company?id=17151"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fasml-fpga-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fasml-fpga-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fasml-fpga-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/asml-fpga-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fasml-fpga-design-engineer"}]}