{"id":1302954,"url":"https://alion.io/job/ast-science-ran-validation-engineer","title":"RAN Validation Engineer","company":{"id":2057930,"name":"AST SpaceMobile","domain":"ast-science.com","url":"https://alion.io/company/ast-science","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"middle","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":25000,"max_usd":53000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":438},"experience_years_min":4,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Cadence Xcelium","optional":true},{"name":"Git","optional":true},{"name":"Python","optional":true},{"name":"Verilog","optional":true},{"name":"VHDL","optional":true},{"name":"Xilinx Vivado","optional":true}],"status":"live","first_seen_at":"2026-08-14T21:40:50Z","employer_posted_date":"2026-08-14","last_verified_at":"2026-09-27T00:27:23Z","board_verified":true,"closed_at":null,"days_open":43,"trust":{"level":"ok","repost_count":0,"flags":["company_stale"],"days_open":42},"description":"AST SpaceMobile is building the first and only global cellular broadband network in space to operate directly with standard, unmodified mobile devices based on our extensive IP and patent portfolio and designed for both commercial and government applications. Our engineers and space scientists are on a mission to eliminate the connectivity gaps faced by today’s five billion mobile subscribers and finally bring broadband to the billions who remain unconnected.\nPosition Overview\n We are seeking a Senior FPGA Verification Engineer with 4-8 years of experience to design, develop, and execute comprehensive verification strategies for complex FPGA designs. This role requires strong hands-on expertise in SystemVerilog and UVM, testbench architecture, and cross-functional collaboration with design and system teams.\nKey Responsibilities:\n\nDevelop and maintain SystemVerilog/UVM-based verification environments for FPGA block-level and top-level designs\nCreate and execute verification plans, directed and constrained-random test scenarios, assertions, and functional coverage\nPerform simulation-based verification of FPGA designs using industry-standard simulators\nDrive debug and root-cause analysis of functional issues and work closely with FPGA RTL designers\nIntegrate and maintain VIPs, scoreboards, checkers, and reference models\nSupport FPGA bring-up, validation, and debug activities on FPGA platforms and evaluation boards\nReview FPGA RTL, verification code, and test plans to ensure quality and completeness\nMentor junior engineers and contribute to FPGA verification best practices\nSupport regression runs, coverage closure, and release signoff\nQualifications\nEducation:\n Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field\nExperience:\n4-8 years of hands-on experience in functional verification\nPreferred Qualifications:\n\nFamiliarity with cadence tools like Xcelium\nFamiliarity with Xilinx Vivado\nExperience with hardware/software co-verification\nKnowledge of high-speed interfaces (AXI, AXI-Stream, DDR, SPI)\nSoft Skills:\n\nStrong analytical and debugging skills\nAbility to work effectively in cross-functional teams\nExcellent written and verbal communication skills\nSelf-driven with the ability to own verification tasks end-to-end\nHigh attention to detail and commitment to quality\nTechnology Stack:\n\nLanguages: SystemVerilog, Verilog, VHDL (working knowledge)\nVerification Methodology: UVM\nSimulation Tools: Xcelium, Questa, VCS\nFPGA Tools: Xilinx Vivado\nDebug Tools: SimVision\nScripting: Python, Tcl, Shell\nVersion Control: Git\nPhysical Requirements\n\nAbility to work in a standard office environment\nAbility to use a computer for extended periods\nOccasional lab work for FPGA bring-up and debug\nThis job description may not be inclusive to the duties and responsibilities listed. Additional tasks may be assigned to the employee from time to time or the scope of the job may change as needed by business demands. \nAST SpaceMobile is an Equal Opportunity, at will Employer; employment is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.","description_format":"text","description_chars":3377,"description_truncated":false,"requirements":{"experience_years_min":4,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Telecommunications"],"lifecycle":[{"event":"open","at":"2026-09-26T12:21:47Z"}],"liveness":{"score":22,"band":"cold","label":"Long shot","p_open":1,"p_active":0.616,"p_room":0.36,"age_days":43,"expected_fill_days":27,"reasons":["conf:3","win:tail","crowd:brand"],"computed_at":"2026-09-27T03:33:52Z"},"pay":null,"html_url":"https://alion.io/job/ast-science-ran-validation-engineer","json_url":"https://alion.io/job/ast-science-ran-validation-engineer.json","meta":{"generated_at":"2026-09-27T03:33:52Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":3332,"day_limit":5000,"remaining_today":1668,"minute_limit":60,"resets_at":"2026-09-28T00:00:00Z"}}}