{"id":1095632,"url":"https://alion.io/job/astera-labs-design-verification-tech-lead-serdesphy-ip","title":"Design Verification Tech Lead- SerDes/PHY IP","company":{"id":178069,"name":"Astera Labs","domain":"asteralabs.com","url":"https://alion.io/company/astera-labs-2","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"B","score":81,"open_postings":48,"ghost_share":0,"stale_share":0.563,"repost_share":0,"time_to_fill_p50_days":77,"computed_at":"2026-11-10T06:52:35Z"}},"role":"Leadership","role_family":"Leadership","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":192000,"max_usd":393000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":1354},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"NVLink","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Cadence Palladium","optional":true},{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"Siemens Veloce","optional":true},{"name":"Synopsys ZeBu","optional":true}],"status":"live","first_seen_at":"2026-09-21T17:11:39Z","employer_posted_date":"2026-10-17","last_verified_at":"2026-11-10T23:04:38Z","board_verified":true,"closed_at":null,"days_open":50,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":50},"description":"Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\nDesign Verification Tech Lead- SerDes/PHY IP\nSan Jose, California, United States\nAstera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\nRole Overview\nAstera Labs is hiring a Principal Design Verification Engineer to own functional verification of our high-speed SerDes/PHY IP - the connectivity engine powering rack-scale AI infrastructure. You will architect verification environments, drive coverage closure, and ensure first-pass silicon success on the analog/digital boundary that defines next-generation AI systems.\nThis is a high-impact, hands-on role at the heart of Astera Labs' hyper-growth story. You'll partner directly with PHY analog/mixed-signal designers, digital architects, and SoC integration teams to verify multi-Gbps SerDes blocks that ship into the world's most advanced AI platforms, including UALink, UCIe, PCIe Gen 6/Gen 7, and Ethernet-based connectivity products.\nKey Responsibilities\nVerification Architecture & Strategy\n\nArchitect UVM-based verification environments for SerDes/PHY IP, including PMA, PCS, and PHY-MAC interface layers\nDefine verification plans, coverage models, and sign-off criteria for high-speed serial link blocks\nDrive methodology decisions across analog/mixed-signal co-simulation, gate-level simulation, and emulation flows\n\nExecution & Coverage Closure\n\nDevelop SystemVerilog/UVM testbenches, sequences, scoreboards, and reference models for multi-Gbps SerDes lanes\nExecute functional, performance, and corner-case verification across equalization, CDR, training, and link bring-up scenarios\nLead coverage analysis and closure, debug failures with designers, and drive regressions to clean tape-out\n\nPhysical Layer & Protocol Verification\n\nVerify PHY behavior against industry specifications including PCIe Gen 6/Gen 7, UALink, UCIe, and Ethernet PHY standards\nModel and validate channel behavior, link training state machines, and analog handoff scenarios\nPartner with analog/AMS designers on Real Number Modeling (RNM) and behavioral models for SerDes blocks\n\nCross-Functional Leadership\n\nMentor junior DV engineers and set technical direction across the verification team\nCollaborate with SoC integration, firmware, post-silicon validation, and customer engineering teams\nContribute to verification IP reuse strategy and tooling improvements across product lines\n\nBasic Qualifications\nBachelor's degree in Electrical Engineering, Computer Engineering, or related field\n5+ years of design verification experience on high-speed SerDes, PHY, or mixed-signal IP\nStrong understanding of the physical layer, including equalization (CTLE, DFE, FFE), CDR, training sequences, and link bring-up\nExpert-level proficiency in SystemVerilog and UVM\nHands-on experience with analog/mixed-signal co-simulation and Real Number Modeling (RNM)\nWorking knowledge of one or more high-speed serial protocols: PCIe, UALink, UCIe, Ethernet, or CXL\nPreferred Qualifications\nMS or PhD in Electrical Engineering or Computer Engineering\nExperience verifying PCIe Gen 6/Gen 7, UALink, or UCIe SerDes/PHY IP\nFamiliarity with emulation platforms (Palladium, Veloce, or ZeBu) and gate-level simulation flows\nScripting proficiency in Python or Perl for verification automation and regression management\nExperience supporting post-silicon bring-up and correlating pre-silicon coverage with silicon results\nProven ability to lead technically across a multi-disciplinary team in a fast-paced environment\nSalary range is $160,000 to $200,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.\nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.","description_format":"text","description_chars":5696,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Servers & Data Center Hardware"],"lifecycle":[{"event":"open","at":"2026-09-21T17:47:57Z"}],"visa":[{"country":"US","licensed_sponsor":true,"adverts_offering_sponsorship_24m":0,"sanctioned_now":false,"evidence":"H-1B filings in 12 months: 77 · green card filings: 7","filings_12m":77,"filings_prev_12m":50,"green_card_filings_12m":7,"median_offered_wage_usd":168155,"route":null,"cap_exempt":false,"checked_at":"2026-11-10T11:34:35+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":0}],"liveness":{"score":45,"band":"ok","label":"Likely open","p_open":1,"p_active":0.619,"p_room":0.72,"age_days":49,"expected_fill_days":77,"reasons":["conf:5","stale_co","velocity","win:mid","crowd:brand"],"computed_at":"2026-11-10T06:52:35Z"},"pay":null,"html_url":"https://alion.io/job/astera-labs-design-verification-tech-lead-serdesphy-ip","json_url":"https://alion.io/job/astera-labs-design-verification-tech-lead-serdesphy-ip.json","meta":{"generated_at":"2026-11-11T01:32:58Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":907,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-12T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.1,"usd":0.01,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":178069},"rest":"https://alion.io/mcp/rest/get_company?id=178069"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fastera-labs-design-verification-tech-lead-serdesphy-ip"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":2,"usd":0.2},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fastera-labs-design-verification-tech-lead-serdesphy-ip"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.1,"usd":0.01},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fastera-labs-design-verification-tech-lead-serdesphy-ip"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/astera-labs-design-verification-tech-lead-serdesphy-ip\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fastera-labs-design-verification-tech-lead-serdesphy-ip"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":1095632}},{"tool":"search_jobs","arguments":{"company":"asteralabs.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":1095632},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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