{"id":919004,"url":"https://alion.io/job/astera-labs-digital-rtl-design-engineer-static-timing-analysis","title":"Synthesis & STA Engineer – High-Speed SerDes","company":{"id":178069,"name":"Astera Labs","domain":"asteralabs.com","url":"https://alion.io/company/astera-labs-2","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"A","score":87,"open_postings":53,"ghost_share":0,"stale_share":0.321,"repost_share":0,"time_to_fill_p50_days":81,"computed_at":"2026-10-16T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":160000,"max":200000,"currency":"USD","period":"year","gross":null,"usd_annual":200000},"salary_estimate":null,"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"Cadence Conformal","optional":false},{"name":"Cadence Tempus","optional":false},{"name":"NVLink","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys PrimeTime","optional":false},{"name":"SystemVerilog","optional":true},{"name":"Verilog","optional":true}],"status":"live","first_seen_at":"2026-09-14T19:51:04Z","employer_posted_date":"2026-10-15","last_verified_at":"2026-10-16T14:42:50Z","board_verified":true,"closed_at":null,"days_open":31,"trust":{"level":"ok","repost_count":1,"flags":[],"days_open":31},"description":"Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\nAbout Astera Labs\nAstera Labs is a global leader in purpose-built connectivity solutions for AI and cloud infrastructure. Our semiconductor-based platforms help solve signal, data, and memory connectivity bottlenecks in the world’s most demanding computing systems.\nOverview\nAs an Astera Labs Synthesis & STA Engineer - High-Speed SerDes you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of high-speed analog/mixed-signal SerDes and connectivity ASICs used in the world's leading cloud service providers, server, and network OEMs. This role requires end-to-end ownership of logic synthesis and static timing analysis across the digital portions of mixed-signal SerDes PHY designs, deep technical expertise in mixed-signal integration, and close collaboration with analog, RTL, physical design, and verification teams to ensure robust timing closure at advanced nodes. \nKey Responsibilities\nPerform RTL synthesis, driving area, power, and timing optimization for digital controller and DSP blocks within high-speed SerDes PHY designs.\nAuthor, develop, and validate SDC constraints from scratch, including clock definitions, generated clocks, multi-frequency/multi-mode constraints, I/O delays, false paths, multicycle paths, and clock-domain crossing exceptions unique to SerDes architectures.\nSet up and manage MMMC (Multi-Mode Multi-Corner) environments to enable accurate and efficient STA across process, voltage, and temperature (PVT) corners.\nDrive timing closure from synthesis through sign-off, ensuring robust timing across digital blocks embedded within analog/mixed-signal SerDes IP and full-chip SoC integration.\nDefine and manage I/O timing budgets and interface constraints between analog and digital boundaries in hierarchical mixed-signal designs.\nApply advanced sign-off methodologies at TSMC 5nm/3nm and below, including OCV/AOCV/POCV and PVT effects relevant to high-speed serial link performance.\nLeverage ETM/ILM libraries for hierarchical timing analysis and correlation of SerDes hard-macro blocks, balancing runtime and accuracy.\nProvide actionable timing feedback at both block and full-chip levels, including root cause analysis, timing debug, and ECO guidance for SerDes digital logic.\nManage large-scale multi-corner/multi-mode STA runs with automation, partitioning, and efficient resource usage, developing scripts and flows to improve turnaround time.\nGenerate and validate timing ECOs, partnering with physical design, analog, and RTL teams for quick closure on high-speed data-path and clock-path issues.\nPartner closely with analog/mixed-signal designers, SerDes architecture, implementation, and verification teams to drive timing convergence and provide sign-off level expertise for PHY-level and chip-level integration.\nCollaborate on clock tree and power domain strategies for SerDes digital blocks, ensuring compatibility with PLL/CDR-generated clocks and multi-supply domains.\nBasic Qualifications\nBachelor's in Electrical Engineering or Computer Science required; Master's preferred.\n≥8 years of experience in synthesis, timing constraints development, STA, and sign-off for high-speed mixed-signal IP in Server, Storage, Networking, or SerDes applications.\nStrong proficiency in writing and debugging SDC constraints, with deep understanding of clock modeling, generated clocks, clock-domain crossings, and exception handling.\nExpertise in STA methodology and timing closure at both block and full-chip level using Synopsys PrimeTime and/or Cadence Tempus.\nStrong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows (Formality/Conformal) in advanced nodes (5nm/3nm and below).\nProficiency with Cadence and/or Synopsys physical design/STA toolchains.\nStrong scripting ability (Tcl, Python, Perl).\nAbility to work independently with strong prioritization and a professional, customer-focused mindset.\nPreferred Experience\n Direct experience with high-speed SerDes, Ethernet PHY (112G/224G), or PCIe/CXL PHY digital controller and DSP timing challenges.\nUnderstanding of analog/mixed-signal integration concerns, including analog-digital interface timing, PLL/DLL/CDR clock structures, and level-shifter/isolation cell constraints.\nKnowledge of ECO methodologies, DFT tools, and test coverage analysis for mixed-signal designs.\nExperience working with IP vendors for both RTL and hard-macro integration, including Liberty (.lib), LEF, and behavioral model characterization.\nSystemVerilog/Verilog proficiency.\nFamiliarity with power-aware synthesis and STA (UPF/CPF flows).\nExperience with high-speed clocking architectures and multi-rate clock domain management typical in SerDes designs.\nSalary and benefits\nThe salary range for this position is $160,000-$200,000. Actual compensation will depend on experience, level, location, and business need. This role may also be eligible for discretionary bonuses, equity incentives, and comprehensive benefits.\nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.","description_format":"text","description_chars":6084,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Equity"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Servers & Data Center Hardware"],"lifecycle":[{"event":"open","at":"2026-09-14T22:51:40Z"},{"event":"close","at":"2026-09-15T19:49:59Z"},{"event":"reopen","at":"2026-10-15T18:21:13Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 77 · green card filings: 7","filings_12m":77,"filings_prev_12m":50,"green_card_filings_12m":7,"median_offered_wage_usd":168155,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":54}],"liveness":{"score":78,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.861,"p_room":0.9,"age_days":31,"expected_fill_days":81,"reasons":["conf:0","velocity","win:mid","comp:brand"],"computed_at":"2026-10-16T05:45:00Z"},"pay":{"stated_usd_annual":200000,"is_top_pay":true},"html_url":"https://alion.io/job/astera-labs-digital-rtl-design-engineer-static-timing-analysis","json_url":"https://alion.io/job/astera-labs-digital-rtl-design-engineer-static-timing-analysis.json","meta":{"generated_at":"2026-10-16T15:58:11Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":314,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-17T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":178069},"rest":"https://alion.io/mcp/rest/get_company?id=178069"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fastera-labs-digital-rtl-design-engineer-static-timing-analysis"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fastera-labs-digital-rtl-design-engineer-static-timing-analysis"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fastera-labs-digital-rtl-design-engineer-static-timing-analysis"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/astera-labs-digital-rtl-design-engineer-static-timing-analysis\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fastera-labs-digital-rtl-design-engineer-static-timing-analysis"}]}