{"id":462312,"url":"https://alion.io/job/astera-labs-distinguished-asic-design-engineer","title":"Distinguished ASIC Design Engineer","company":{"id":178069,"name":"Astera Labs","domain":"asteralabs.com","url":"https://alion.io/company/astera-labs-2","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"B","score":80,"open_postings":58,"ghost_share":0,"stale_share":0.586,"repost_share":0,"time_to_fill_p50_days":78,"computed_at":"2026-10-07T05:47:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"explicit","locations":["Germany"],"countries":["DE"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":116000,"max_usd":275000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":566},"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"InfiniBand","optional":false},{"name":"NVLink","optional":false},{"name":"HPC","optional":true}],"status":"live","first_seen_at":"2026-08-02T12:44:18Z","employer_posted_date":"2026-09-24","last_verified_at":"2026-10-07T23:43:56Z","board_verified":true,"closed_at":null,"days_open":66,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":66},"description":"Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\nDistinguished ASIC Design Engineer/ Senior Principal\nLocation: Germany (on-site)\nRole Overview\nAstera Labs is building purpose-built silicon for rack-scale AI infrastructure. As a Distinguished Engineer, you will be a senior technical leader driving ASIC design for next-generation Ethernet and Scale-Up (ESUN) connectivity products.\nYou will set technical direction across the full ASIC design flow, spanning high-speed Ethernet, UALink, UCIe, and PCIe Gen 6/7. You will solve complex scale-up networking challenges, mentor senior engineers, and turn ambitious product goals into robust, manufacturable silicon.\nTechnical Leadership & Architecture\nDefine and drive ASIC architecture for Ethernet/ESUN connectivity products across UALink, UCIe, PCIe Gen 6/7, and Ethernet.\nLead architecture and microarchitecture for high-performance Ethernet controllers, MACs, NIC datapaths, packet processing pipelines, and AI interconnect fabrics.\nDefine scalable, low-latency, high-bandwidth data movement, scheduling, buffering, congestion management, QoS, reliability, and flow control.\nArchitect hardware acceleration for NIC functions, RDMA, DMA, virtualization, and protocol offloads.\nLead tradeoff analysis across performance, power, area, latency, scalability, resiliency, and programmability.\nServe as a technical authority across digital, networking, and system domains.\nASIC Design & Execution\nLead RTL design and microarchitecture development for Ethernet controllers, MACs, NIC datapaths, protocol engines, and AI networking subsystems.\nDesign packet processing architectures, DMA engines, queue management, scheduling, buffering, and memory subsystem interfaces.\nDevelop hardware mechanisms for RDMA, zero-copy data movement, congestion control, transport reliability, and protocol acceleration.\nDesign scalable architectures supporting virtualization, multi-tenant isolation, traffic management, and quality of service.\nPartner with firmware and software teams to define hardware/software interfaces for initialization, management, telemetry, performance monitoring, and diagnostics.\nDrive execution from architecture through RTL, integration, verification, tapeout, and post-silicon bring-up.\nPartner cross-functionally to meet performance, timing, power, area, manufacturability, and reliability targets.\nBasic Qualifications\nBachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.\n15+ years of ASIC/SoC design experience, with a track record of delivering complex, high-speed networking or connectivity silicon from architecture through production.\nDeep expertise in RTL design and microarchitecture for high-performance networking and connectivity ASICs.\nExtensive experience designing Ethernet controllers, MACs, NIC architectures, packet processing engines, or network interface subsystems.\nStrong understanding of RDMA architectures and transport protocols such as RoCE, InfiniBand concepts, or similar low-latency networking technologies.\nExperience designing hardware for packet parsing, scheduling, buffering, DMA, queue management, flow control, congestion management, and transport acceleration.\nStrong understanding of high-speed interconnects and protocols, including Ethernet, PCIe, and AI scale-up fabrics.\nHands-on experience across the complete ASIC development flow, including architecture, RTL design, integration, synthesis, timing closure, physical implementation, tapeout, and post-silicon validation.\nDemonstrated technical leadership across multiple teams and product programs.\nPreferred Qualifications\nMaster’s or PhD in Electrical Engineering, Computer Engineering, or a related technical discipline.\nDirect experience with UALink, UCIe, PCIe Gen 6/7, and/or advanced Ethernet architectures and protocols.\nExperience designing Ethernet MACs, controllers, SmartNICs, DPUs, NICs, switch datapaths, or packet processing engines.\nExperience developing Ethernet-based scale-up networking solutions for AI and HPC systems.\nExperience leading architecture or design for multiple successful advanced-node ASIC tapeouts.\nExcellent communication, collaboration, and mentorship skills.\nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with 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