{"id":462314,"url":"https://alion.io/job/astera-labs-distinguished-formal-verification","title":"Distinguished Formal Verification","company":{"id":178069,"name":"Astera Labs","domain":"asteralabs.com","url":"https://alion.io/company/astera-labs-2","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"A","score":87,"open_postings":53,"ghost_share":0,"stale_share":0.302,"repost_share":0,"time_to_fill_p50_days":78,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":186000,"max_usd":353000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":576},"experience_years_min":18,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"NVLink","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"Cadence JasperGold","optional":true},{"name":"CI/CD","optional":true},{"name":"Synopsys VC Formal","optional":true}],"status":"live","first_seen_at":"2026-02-23T18:43:57Z","employer_posted_date":"2026-09-23","last_verified_at":"2026-10-18T04:48:23Z","board_verified":true,"closed_at":null,"days_open":236,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":235},"description":"Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\nAstera Labs is seeking a Distinguished Engineer, Formal Verification to join our world-class engineering team in San Jose, California. As a hyper-growth leader in AI infrastructure connectivity, we're revolutionizing how data centers handle explosive AI workloads through cutting-edge PCIe Gen 6/7, CXL, Ethernet, UCIe, and UALink technologies. This is a rare opportunity to shape the formal verification strategy across our entire product portfolio while working on the most advanced connectivity solutions powering the AI revolution.\nIn this highly strategic role, you'll serve as Astera Labs' technical authority on formal verification, defining methodologies and best practices that ensure the highest quality standards across all our next-generation connectivity products. You'll work at the intersection of innovation and reliability, leading efforts to catch critical corner-case bugs that traditional verification methods miss, while mentoring a global team of engineers and representing Astera Labs as a thought leader in the formal verification community. This position offers exceptional scope for impact-your work will directly enable the rack-scale AI infrastructure that's transforming cloud computing and enterprise data centers worldwide.\nKey Responsibilities\nStrategic Leadership & Methodology Development\nDefine and evolve formal verification strategy, methodologies, and best practices across all product lines for PCIe, CXL, Ethernet, UCIe, and UALink protocols\nServe as technical authority on formal verification, providing expert guidance to engineering leadership on risk mitigation and design quality\nRepresent Astera Labs in industry forums, standards bodies, and technical conferences as a thought leader in formal verification\nDrive cross-functional collaboration to influence technical direction across the organization\nTechnical Execution & Innovation\nDevelop detailed formal verification test plans based on design specifications and collaborate with design teams to refine micro-architecture specifications\nIdentify key logic components and critical micro-architectural properties essential for ensuring design correctness\nImplement formal verification models, abstractions, assertions, and utilize assertion-based model checking to detect corner-case bugs\nApply complexity reduction techniques using industry-standard EDA tools to achieve proof convergence or sufficient depth\nDevelop and maintain scripts to enhance FV productivity and streamline verification processes\n Team Development & Cross-Functional Partnership\nMentor Principal and Lead Engineers across global sites in advanced formal verification techniques\nAssist design teams with the implementation of assertions and formal verification testbenches for RTL at unit/block levels\nParticipate in design reviews and collaborate with design teams to optimize design quality and performance, power, area (PPA) metrics based on formal analysis feedback\nPrepare and deliver customer meetings and executive presentations with minimal supervision\nBasic Qualifications\nBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field\n15+ years of experience in formal verification or 18+ years of experience in traditional design verification with significant formal verification specialization\nStrong proficiency in SystemVerilog/Verilog with deep understanding of hardware design verification\nAdvanced scripting abilities with Python or Perl for automation and productivity enhancement\nProven ability to manage and prioritize multiple high-impact tasks in a dynamic, fast-paced environment with minimal supervision\nStrong cross-functional collaboration skills with demonstrated ability to influence technical direction and drive consensus\nEntrepreneurial mindset with proactive, customer-focused attitude and ability to think and act quickly while maintaining high quality standards\nPreferred Qualifications\nMaster's or PhD in Electrical Engineering, Computer Engineering, Computer Science, or Mathematics with focus on formal methods or verification\nHands-on experience with formal verification tools such as Synopsys VCFormal and Cadence JasperGold\nExperience with both bug hunting and static proof verification techniques\nFamiliarity with automating formal verification workflows within a CI/CD environment\nDeep knowledge of high-speed serial protocols: PCIe Gen 4/5/6/7, CXL, Ethernet (100G/400G/800G), UCIe, UALink\nParticipation in industry standards bodies (PCI-SIG, CXL Consortium, IEEE, UCIe Consortium)\nPatents or publications in formal verification or hardware verification methodologies\nTrack record of recruiting, mentoring, and developing formal verification talent across distributed teams\nSalary range is $230,000 to $285,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.","description_format":"text","description_chars":5982,"description_truncated":false,"requirements":{"experience_years_min":18,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Servers & Data Center Hardware"],"lifecycle":[{"event":"open","at":"2026-09-06T11:26:14Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 77 · green card filings: 7","filings_12m":77,"filings_prev_12m":50,"green_card_filings_12m":7,"median_offered_wage_usd":168155,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":54}],"liveness":{"score":15,"band":"cold","label":"Long shot","p_open":1,"p_active":0.552,"p_room":0.28,"age_days":235,"expected_fill_days":78,"reasons":["conf:3","velocity","win:tail","crowd:brand"],"computed_at":"2026-10-17T05:46:00Z"},"pay":null,"html_url":"https://alion.io/job/astera-labs-distinguished-formal-verification","json_url":"https://alion.io/job/astera-labs-distinguished-formal-verification.json","meta":{"generated_at":"2026-10-18T04:54:30Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":7414,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-19T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":178069},"rest":"https://alion.io/mcp/rest/get_company?id=178069"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fastera-labs-distinguished-formal-verification"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fastera-labs-distinguished-formal-verification"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fastera-labs-distinguished-formal-verification"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/astera-labs-distinguished-formal-verification\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fastera-labs-distinguished-formal-verification"}]}