{"id":2952414,"url":"https://alion.io/job/astera-labs-firmware-engineer","title":"Firmware Engineer","company":{"id":178069,"name":"Astera Labs","domain":"asteralabs.com","url":"https://alion.io/company/astera-labs-2","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"B","score":82,"open_postings":52,"ghost_share":0,"stale_share":0.519,"repost_share":0,"time_to_fill_p50_days":77,"computed_at":"2026-10-28T05:59:10Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":156000,"max_usd":287000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":1517},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"NVLink","optional":false},{"name":"Python","optional":false},{"name":"RTOS","optional":true}],"status":"live","first_seen_at":"2026-10-20T16:50:33Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-29T00:42:27Z","board_verified":true,"closed_at":null,"days_open":8,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":8},"description":"Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\nJob Description: \nThe mission of this role is to architect and develop firmware and microcontroller subsystems for Astera Labs’ SoC and systems products. Firmware is responsible for implementing the major differentiating features of Astera Labs’ products. As such, firmware is considered equally important to the hardware, and the firmware team is often customer-facing accordingly to ensure the customer's needs are fully comprehended. \nBasic qualifications: \nStrong academic and technical background in electrical engineering. At a minimum, a Bachelor’s in EE or Computer Science is required. \nMinimum 5 years' experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications. \nExperience developing firmware to execute with on-chip microcontrollers and C-language software development kits (SDKs) to execute on system host CPUs and embedded microprocessors. \nExperience working with logic designers to implement and test HW-SW interfaces on complex SoCs. \nProfessional attitude with the ability to prioritize a dynamic list of multiple tasks, and to work with minimal guidance and supervision. \nEntrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind! \nCan start immediately. \nRequired experience: \nHigh level of proficiency in C (preferred) or C++, including development of C-based SDKs and firmware. \nProficient in Python for scripting. \nAbility to design, implement, and write unit-level tests. \nWorking knowledge of software build environments, gcc/make. \nExperience with developer workflows, SCM (preferably git), code reviews, CI. \nHands-on experience with Server, Storage, and/or Networking equipment. \nFamiliarity with SoC interfaces to various HW blocks, on-chip memory interfaces, and other similar interfaces that are common to chip design. \nPreferred experience: \nFirmware development experience using RTOS. \nExperience developing boot-ROM and familiarity working in pre-Silicon environments (Simulation and emulation). \nExperience with secure boot flows (authentication, attestation & standards like DICE, Caliptra) is an asset. \nWe know that creativity and innovation happen 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