{"id":462333,"url":"https://alion.io/job/astera-labs-ip-design-verification-director","title":"IP Design Verification Director","company":{"id":178069,"name":"Astera Labs","domain":"asteralabs.com","url":"https://alion.io/company/astera-labs-2","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"A","score":87,"open_postings":53,"ghost_share":0,"stale_share":0.302,"repost_share":0,"time_to_fill_p50_days":78,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Leadership","role_family":"Leadership","seniority":"head","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":72000,"max_usd":191000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":37},"experience_years_min":20,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"NVLink","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-03-05T21:50:48Z","employer_posted_date":"2026-09-23","last_verified_at":"2026-10-19T04:03:26Z","board_verified":true,"closed_at":null,"days_open":227,"trust":{"level":"ok","repost_count":0,"flags":[],"days_open":227},"description":"Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\nJob Title: Director of Design Verification\nOverview\nWe are seeking a seasoned Director of Design Verification with 20+ years of experience to lead verification for a flagship product in our portfolio. This is a hands-on leadership role where you will define the verification strategy, oversee execution, and ensure first-pass silicon success for complex SoC designs in server, storage, and networking domains.\nKey Responsibilities\nOwn and drive the end-to-end verification methodology for a specific product line.\nLead, mentor, and grow a team of engineers, fostering technical excellence and innovation.\nGuide verification of industry-standard protocols such as PCIe and CXL across Physical, Link, and Transaction layers.\nChampion advanced methodologies (UVM, formal verification, AI-augmented flows) to accelerate coverage closure and improve efficiency.\nCollaborate closely with RTL design, architecture, and software teams to debug, refine, and optimize verification processes.\nRepresent verification in executive reviews, customer engagements, and industry forums.\nShape workforce transformation by building hybrid skill sets and preparing the team for AI-driven verification challenges of the 2030s.\nQualifications\nBachelor’s degree in Electrical or Computer Engineering (Master’s preferred).\n15+ years of experience in design verification, with a proven track record of leading teams and delivering complex SoC/silicon products.\nDeep expertise in PCIe/CXL protocols (Gen3 and above) and experience with third-party Verification IPs.\nStrong background in UVM-based test plan development, assertions, coverage analysis, and abstraction layer design.\nDemonstrated ability to manage priorities, engage with stakeholders, and drive organizational success.\nRequired Experience\nHands-on expertise with Verification IPs for PCIe/CXL (Gen3 and above).\nDeep experience in UVM-based test plan development, sequence generation, and coverage analysis.\nStrong background in writing assertions, cover properties, and analyzing coverage data.\nExperience in developing VIP abstraction layers to simplify and scale verification deployments.\nPreferred Experience\nExpertise in verifying PCIe/CXL Physical, Link, and Transaction layers, including compliance for EP/RC.\nExperience with buffering, queuing, and QoS in complex NoC-based SoCs.\nSystem-level performance analysis on switching fabrics.\nFamiliarity with AI-driven verification methodologies and workforce transformation strategies.\nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with 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