{"id":588271,"url":"https://alion.io/job/astera-labs-lead-logic-design-for-ualink-ipsubsystem-engineer","title":"Lead Logic Design Engineer","company":{"id":178069,"name":"Astera Labs","domain":"asteralabs.com","url":"https://alion.io/company/astera-labs-2","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"B","score":81,"open_postings":51,"ghost_share":0,"stale_share":0.549,"repost_share":0,"time_to_fill_p50_days":73,"computed_at":"2026-10-31T05:58:55Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":33000,"max_usd":74000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":796},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"NVLink","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-09-10T08:35:10Z","employer_posted_date":"2026-09-23","last_verified_at":"2026-11-01T02:28:06Z","board_verified":true,"closed_at":null,"days_open":51,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":51},"description":"Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\nLead Logic Design Engineer - UALink IP/Subsystem \nExperience \n6-10 years \nJob Summary \nLead RTL and microarchitecture development for UALink-based IP/subsystems, focusing on high-bandwidth, low-latency data movement and scalable interconnect design. \nKey Responsibilities \nLead UALink IP/subsystem RTL development. \nTranslate protocol requirements into detailed microarchitecture. \nDesign high-performance control and data-path logic. \nWork on buffering, arbitration, flow control, ordering, and error handling. \nDevelop and review SystemVerilog RTL. \nDrive performance, area, power, and latency optimization. \nCollaborate with verification, SoC integration, and physical design teams. \nDebug complex functional and integration issues. \nReview RTL and mentor engineers. \nSupport silicon debug and issue resolution. \nRequired Skills \nStrong RTL and microarchitecture experience. \nExperience with high-speed interconnects. \nStrong understanding of data movement, flow control, arbitration, and buffering. \nExcellent SystemVerilog/Verilog skills. \nExperience with CDC, lint, synthesis, and timing. \nStrong debugging and technical leadership skills. \nPreferred \nDirect UALink experience. \nExperience with PCIe, CXL, CHI, CCIX, Ethernet, or similar technologies. \nExperience with AI/accelerator or high-performance compute SoCs. \nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with 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