{"id":462342,"url":"https://alion.io/job/astera-labs-pcie-post-silicon-validation-engineer","title":"System Validation Engineer","company":{"id":178069,"name":"Astera Labs","domain":"asteralabs.com","url":"https://alion.io/company/astera-labs-2","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"B","score":81,"open_postings":48,"ghost_share":0,"stale_share":0.563,"repost_share":0,"time_to_fill_p50_days":77,"computed_at":"2026-11-11T05:49:22Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Haifa, Israel"],"countries":["IL"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":111000,"max_usd":253000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":1936},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Linux","optional":false},{"name":"NVLink","optional":false},{"name":"Python","optional":false}],"status":"live","first_seen_at":"2026-08-17T08:43:59Z","employer_posted_date":"2026-10-17","last_verified_at":"2026-11-12T00:14:11Z","board_verified":true,"closed_at":null,"days_open":86,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":86},"description":"Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\nWe are looking for a Post-Silicon Validation Engineer with strong hands-on experience in PCIe link bring-up, physical-layer debug, and silicon validation. Engineer will work closely with Design, Architecture, Firmware, Software, Engineering teams.\nKey Responsibilities\nPerform hands-on post-silicon validation\n\nDebug PCIe link issues including link training, LTSSM, equalization, recovery, resets, and link stability.\nAnalyze PCIe state-machine traces, protocol traces, registers, logs, eye diagrams, and lab measurements.\nDrive complex issues from initial failure through root-cause analysis and final resolution.\nWork closely with silicon, firmware, software, architecture, and signal-integrity engineers to isolate issues across HW/FW/SW boundaries.\nValidate PCIe functionality across different generations, platforms, configurations, and operating conditions.\nDevelop and execute PCIe validation plans, stress tests, corner-case scenarios, and interoperability tests.\nDevelop automation to improve validation coverage, debug efficiency, and regression testing.\n\nRequired Qualifications\nBS/MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.\n5+ years of engineering experience in silicon validation, post-silicon debug, or high-speed interface development.\nStrong hands-on knowledge of PCIe architecture and protocol.\nExperience working with PCIe analyzers, state traces, registers, logs, eye diagrams, and/or signal-integrity measurements.\n\nStrong problem-solving skills and ability to independently drive issues to root cause.\nExperience working across hardware, firmware, and software boundaries.\nGood scripting/programming skills, preferably Python \n\nGood Linux knowledge and experience with Linux PCIe debug tools.\nStrong communication and collaboration skills.\nPreferred Qualifications\nExperience with PCIe Gen4/Gen5/Gen6/Gen7\n\nHands-on experience with PCIe PHY, SerDes, equalization, lane margining, or signal integrity.\nExperience with PCIe compliance and interoperability testing.\nExperience debugging intermittent, marginal, thermal-sensitive, or corner-case PCIe failures.\nExperience with PCIe switches, or networking/accelerator platforms.\n\nPractical experience using AI/ML tools for engineering debug and automation.\n\nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.","description_format":"text","description_chars":3358,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":true},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Servers & Data Center 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