{"id":3192834,"url":"https://alion.io/job/astera-labs-physical-design-engineering-director","title":"Physical Design Engineering Director","company":{"id":178069,"name":"Astera Labs","domain":"asteralabs.com","url":"https://alion.io/company/astera-labs-2","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"B","score":82,"open_postings":54,"ghost_share":0,"stale_share":0.537,"repost_share":0,"time_to_fill_p50_days":73,"computed_at":"2026-10-25T05:49:26Z"}},"role":"Leadership","role_family":"Leadership","seniority":"head","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Toronto, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":119000,"max_usd":219000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":87},"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Innovus","optional":false},{"name":"NVLink","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys Fusion Compiler","optional":false},{"name":"AI Agents","optional":true}],"status":"live","first_seen_at":"2026-10-24T00:08:11Z","employer_posted_date":"2026-10-24","last_verified_at":"2026-10-26T04:23:14Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\nRole Overview\nAstera Labs is seeking aPhysical Design Engineering Director to lead a team of physical design engineers at our Toronto site, driving the implementation of connectivity ASICs within our Signal Connectivity Group. This group is responsible for products that enable high-speed serial connectivity including PCIe retimers, Ethernet retimers, and signal conditioning solutions deployed across the world's largest AI clusters and hyperscale data centers.\nAs an Physical Design Engineering Director, you will combine hands-on technical leadership with people management, owning physical design execution from RTL to GDSII while building and mentoring a high-performing team. You will drive floorplanning, place-and-route, timing closure, and sign-off for complex designs requiring deep understanding of high-speed physical layer interfaces and SerDes integration at TSMC advanced nodes. This role is fully on-site at our Toronto location.\nBasic Qualifications\nBachelor's degree in Electrical Engineering, Computer Engineering, or a related field; Master's preferred.\n15+ years of experience in physical design implementation of complex SoCs at advanced nodes (7nm and below).\n5+ years of experience leading teams or projects with demonstrated ability to mentor and develop engineers.\nHands-on expertise across the physical design flow: synthesis, place-and-route, CTS, extraction, timing closure, EM-IR, DRC/LVS, and equivalence checking.\nProficiency with Cadence Innovus and/or Synopsys Fusion Compiler/ICC2 and supporting toolchains.\nStrong scripting ability in Tcl, Python, and/or Perl.\nProfessional attitude with the ability to prioritize a dynamic list of tasks, plan and prepare for customer meetings in advance, and work with minimal guidance.\nEntrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind! \nRequired Experience\nBuild, lead, and mentor a physical design team, owning Physical Design execution and team development for Signal Connectivity Group products.\nDrive block and top-level physical design implementation from floorplan through tapeout for retimer and signal conditioning ASICs.\nCollaborate with RTL, DFT, STA, EMIR, and verification teams to drive design convergence from synthesis through sign-off.\nWork with IP vendors for both RTL and hard-macro integration, ensuring placement constraints and routing guidelines are met.\nDrive team execution, hiring, career development, and sprint planning for the Toronto PD team.\nEstablish physical design best practices, flow improvements, and quality checks to scale execution across multiple concurrent programs.\nCoordinate with global PD teams (San Jose, Irvine, Bangalore) to ensure consistent methodology and design quality.\nExperience with Cadence and/or Synopsys physical design tools/flows.\nPreferred Experience/Nice to Have\nDeep understanding of high-speed SerDes physical layer, including equalization, CDR, and signal integrity considerations impacting physical design.\nKnowledge of physical layer timing challenges specific to high-speed serial interfaces.\nTrack record of building and scaling physical design teams through multiple tapeouts.\nKnowledge of agentic AI solutions for EDA automation.\nBase salary range is CAD 200,000 to CAD 250,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives, and benefits.\nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.","description_format":"text","description_chars":4486,"description_truncated":false,"requirements":{"experience_years_min":15,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Servers & Data Center Hardware"],"lifecycle":[{"event":"open","at":"2026-10-24T02:50:12Z"}],"visa":[{"country":"CA","licensed_sponsor":true,"evidence":"Positions approved through LMIA in 12 months: 1","filings_12m":1,"filings_prev_12m":4,"green_card_filings_12m":null,"median_offered_wage_usd":null,"route":"Global Talent Stream","cap_exempt":false,"checked_at":"2026-10-03T21:10:52+00:00","sources":["ESDC: employers issued a positive LMIA"],"filings_for_role_12m":0}],"liveness":{"score":63,"band":"ok","label":"Likely open","p_open":1,"p_active":0.632,"p_room":1,"age_days":1,"expected_fill_days":73,"reasons":["conf:0","stale_co","velocity","win:early","comp:brand"],"computed_at":"2026-10-25T05:49:26Z"},"pay":null,"html_url":"https://alion.io/job/astera-labs-physical-design-engineering-director","json_url":"https://alion.io/job/astera-labs-physical-design-engineering-director.json","meta":{"generated_at":"2026-10-26T05:34:57Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":7468,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-27T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":178069},"rest":"https://alion.io/mcp/rest/get_company?id=178069"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fastera-labs-physical-design-engineering-director"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fastera-labs-physical-design-engineering-director"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fastera-labs-physical-design-engineering-director"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/astera-labs-physical-design-engineering-director\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fastera-labs-physical-design-engineering-director"}]}