{"id":1672599,"url":"https://alion.io/job/astera-labs-principal-digital-design-engineer-4","title":"Principal Digital Design Engineer","company":{"id":178069,"name":"Astera Labs","domain":"asteralabs.com","url":"https://alion.io/company/astera-labs-2","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"A","score":88,"open_postings":54,"ghost_share":0,"stale_share":0.278,"repost_share":0,"time_to_fill_p50_days":78,"computed_at":"2026-10-21T05:46:15Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":185000,"max":230000,"currency":"USD","period":"year","gross":null,"usd_annual":230000},"salary_estimate":null,"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"InfiniBand","optional":false},{"name":"NVLink","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-09-14T22:05:04Z","employer_posted_date":"2026-09-23","last_verified_at":"2026-10-21T18:29:22Z","board_verified":true,"closed_at":null,"days_open":36,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":36},"description":"Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\nPrincipal Digital Design Engineer:\nOverview\nJoin our team as Principal Digital Design Engineer to architect and implement next-generation digital designs for high-performance connectivity solutions. You'll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, PD and DFT teams to deliver high-performance products in a fast-paced, collaborative environment.\nKey Responsibilities\nDevelop and implement complex digital blocks and subsystems by defining micro-architecture and driving digital design.\nCollaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues.\nLead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance.\nWork closely with post-silicon teams to facilitate silicon bring-up and debug.\nMentor junior engineers to develop their technical skills and expertise.\nActively contribute to the development and improvement of silicon development processes.\nDrive designs to production, ensuring accountability for quality, schedule, and overall design success.\nRequired Qualifications:\nEducation & Experience:\nBachelor’s degree in electrical engineering or equivalent.\n8+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets\nDigital Design Expertise:\nArchitecture definition and micro-architecture development\nRTL coding, functional simulation, and synthesis\nTiming closure and gate-level simulation (GLS)\nDesign for test (DFT) implementation\nProduction experience with advanced CMOS nodes (≤7nm)\nProtocols & Integration:\nDeep expertise in at least one high-speed protocol-PCIe, Ethernet, InfiniBand, DDR, or similar\nThird-party IP integration and verification.\nBlock-level design ownership from architecture through GDS\nTools & Methodologies:\nProficiency with Cadence and/or Synopsys digital design flows\nFamiliarity with UVM-based verification methodologies.\nSilicon bring-up, debug, and failure analysis expertise\nProfessional Attributes:\nStrong work ethic with the ability to balance multiple priorities in a dynamic environment\nExcellent communication and collaboration skills; comfortable working cross-functionally with global teams\nSelf-directed learner who thrives with minimal supervision and adapts quickly to changing requirements\nCustomer-focused mindset with ability to translate business needs into technical excellence\nPreferred Qualifications\nTrack record of delivering multiple high-performance designs to production in data-center environments\nHands-on collaboration with embedded firmware teams; deep understanding of firmware development challenges and constraints\nFamiliarity with standard embedded processor subsystems (RISC-V, Arm, etc.)\nProven contributions to design methodology, CAD automation, or design infrastructure to improve productivity or design quality\nThe base salary range is $185,000.00 USD - $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. \nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.","description_format":"text","description_chars":4199,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Servers & Data Center Hardware"],"lifecycle":[{"event":"open","at":"2026-10-02T07:20:55Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 77 · green card filings: 7","filings_12m":77,"filings_prev_12m":50,"green_card_filings_12m":7,"median_offered_wage_usd":168155,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":0}],"liveness":{"score":80,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.894,"p_room":0.9,"age_days":36,"expected_fill_days":78,"reasons":["conf:1","velocity","win:mid","comp:brand"],"computed_at":"2026-10-21T05:46:15Z"},"pay":{"stated_usd_annual":230000,"is_top_pay":true},"html_url":"https://alion.io/job/astera-labs-principal-digital-design-engineer-4","json_url":"https://alion.io/job/astera-labs-principal-digital-design-engineer-4.json","meta":{"generated_at":"2026-10-21T19:55:52Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":28242,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-22T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":178069},"rest":"https://alion.io/mcp/rest/get_company?id=178069"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fastera-labs-principal-digital-design-engineer-4"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fastera-labs-principal-digital-design-engineer-4"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fastera-labs-principal-digital-design-engineer-4"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/astera-labs-principal-digital-design-engineer-4\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fastera-labs-principal-digital-design-engineer-4"}]}