{"id":3798157,"url":"https://alion.io/job/astera-labs-principal-formal-verification-engineer","title":"Principal Formal Verification Engineer","company":{"id":178069,"name":"Astera Labs","domain":"asteralabs.com","url":"https://alion.io/company/astera-labs-2","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"B","score":81,"open_postings":49,"ghost_share":0,"stale_share":0.571,"repost_share":0,"time_to_fill_p50_days":77,"computed_at":"2026-11-09T06:03:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"NVLink","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Cadence JasperGold","optional":true},{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"Synopsys VC Formal","optional":true}],"status":"live","first_seen_at":"2026-11-05T08:29:50Z","employer_posted_date":"2026-11-05","last_verified_at":"2026-11-09T05:05:13Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\nPrincipal Formal Verification Engineer\nRole Overview\nWe are looking for a Principal Formal Verification Engineer with 10+ years of experience to lead formal verification efforts for complex semiconductor and silicon designs. This role will be responsible for driving verification strategy, improving design quality, and mentoring engineers while working closely with design, architecture, and validation teams.\nKey Responsibilities\nLead formal verification activities for block-level and subsystem-level designs.\nDefine formal verification plans, methodologies, and closure criteria for complex digital designs.\nDevelop and execute formal verification environments, assertions, properties, and checkers.\nCollaborate with RTL designers, architects, and verification teams to understand design intent and verification requirements.\nIdentify functional corner cases, protocol issues, and design bugs early in the development cycle.\nDrive bug triage, root-cause analysis, and resolution with cross-functional teams.\nImprove verification productivity through reusable flows, automation, and best practices.\nMentor and guide junior verification engineers and contribute to team capability building.\nSupport project planning by estimating verification effort, tracking progress, and highlighting risks.\nRequired Qualifications\nBachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.\n10 years of experience in formal verification, functional verification, or related semiconductor verification roles.\nStrong understanding of digital design fundamentals, RTL design, and verification concepts.\nHands-on experience with formal verification tools and methodologies.\nStrong knowledge of SystemVerilog, assertions, and verification techniques.\nExperience verifying complex protocols, control logic, and SoC or subsystem-level designs.\nGood debugging and analytical problem-solving skills.\nExperience leading technical efforts or mentoring team members.\nStrong communication and cross-functional collaboration skills.\nPreferred Qualifications\nExperience with industry-standard formal tools such as JasperGold, VC Formal, or equivalent.\nKnowledge of AMBA protocols such as AXI, AHB, or APB.\nFamiliarity with low-power verification, CDC, RDC, or equivalence checking.\nExperience in scripting using Python, Perl, Tcl, or shell.\nExposure to emulation, simulation, and overall verification lifecycle is a plus.\nPrior experience in high-speed interconnect, networking, PCIe, CXL, DDR, or similar domains is an advantage.\nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with 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