{"id":1923815,"url":"https://alion.io/job/astera-labs-principal-fwsw-engineer","title":"Principal FW/SW Engineer","company":{"id":178069,"name":"Astera Labs","domain":"asteralabs.com","url":"https://alion.io/company/astera-labs-2","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"B","score":82,"open_postings":53,"ghost_share":0,"stale_share":0.528,"repost_share":0,"time_to_fill_p50_days":78,"computed_at":"2026-10-14T06:34:16Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Toronto, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":89000,"max_usd":165000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":75},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Bash","optional":false},{"name":"C++","optional":false},{"name":"Embedded C","optional":false},{"name":"Git","optional":false},{"name":"Linux","optional":false},{"name":"NVLink","optional":false},{"name":"C","optional":true},{"name":"CI/CD","optional":true},{"name":"Jenkins","optional":true},{"name":"Python","optional":true},{"name":"RTOS","optional":true}],"status":"live","first_seen_at":"2026-10-05T17:58:01Z","employer_posted_date":"2026-10-07","last_verified_at":"2026-10-14T12:42:50Z","board_verified":true,"closed_at":null,"days_open":8,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":8},"description":"Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\nPrincipal Engineer - Embedded Firmware & Software \nLocation: Toronto or Ottawa, Ontario (Remote) \nTravel: Occasional travel to Astera Labs’ San Jose headquarters, approximately twiceper year, for chip bring-up and project coordination \nEmployment: Full-time \nRole Overview \nJoin Astera Labs’ Signal Connectivity Engineering team as a Principal Engineershaping the firmware and software that makes advanced connectivity products adaptive, reliable, and production-ready. You will own embedded software across analog connectivity and Ethernet retimerplatforms, from low-level hardware abstraction and calibration through link management, diagnostics, validation, and customer deployment. \nThis is a high-impact role at the intersection of embedded systems, mixed-signal hardware, and Ethernet physical-layer behavior. You will work across architecture, lab debug, automation, and customer integration while partnering with silicon, analog, systems, validation, and applications teams. Your work will help deliver purpose-built connectivity for rack-scale AI infrastructure as Astera Labs continues to scale. \nKey Responsibilities \nFirmware Architecture & Product Ownership \nOwn the embedded firmware stack from hardware abstraction and device drivers through management interfaces, diagnostics, and customer-facing APIs. \nDesign firmware for adaptive equalization, gain control, calibration, link training, PLL/CDR feedback, thermal management, and device telemetry. \nArchitect control algorithms, state machines, and tuning flows that manage analog and high-speed interfaces across process, voltage, and temperature variation. \nDefine software quality gates, validation criteria, and release practices from pre-silicon planning through production deployment. \nEthernet, Lab Debug & System Integration \nDebug firmware behavior across Ethernet configurations, link states, and failure modes by tracing interactions among Layer 1 PHY, SERDES, FEC/PCS, MAC, retimer, and gearbox components. \nInvestigate register accesses, embedded SDK behavior, link state machines, PHY telemetry, logs, and real-hardware measurements to identifyroot causes and deliver targeted fixes. \nPartner with system validation to develop test plans, automate characterization flows, and verify firmware across corner cases and product configurations. \nSupport customerbring-up, field issue triage, and deployment readiness in collaboration with applications, platform, and silicon teams. \nTechnical Leadership & Collaboration \nSet technical direction, lead architecture and tradeoff discussions, and balance performance, code size, maintainability, and time to market. \nServe as a technical authority for mixed-signal firmware, analog control behavior, Ethernet physical-layer debug, and hardware/software integration. \nLead design reviews, implementation, code reviews, and difficult debug efforts across firmware, analog, silicon, systems, validation, and applications teams. \nMentor engineers and help build the team through recruiting, onboarding, and technical development; peoplemanagement or a senior technical-lead path may be available as the organization grows. \nBasic Qualifications \nBachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a relatedfield. \n8-12 years of experience developing embedded firmware or software for resource-constrained systems, with ownership from architecture through production. \nStrong embedded C/C++ skills and deep knowledge of microcontroller architecture, memory-mapped peripherals, interrupt handling, and bare-metal firmware. \nHands-on experience with Ethernet or high-speed connectivity devices, including Layer 1 PHYs, SERDES, retimers, gearboxes, NICs, switches, or related systems. \nSolid understanding of physical-layer behavior, link state machines, register-level debug, and hardware/software integration. \nExperience with feedback systems, adaptive algorithms, calibration, or tuning of analog or mixed-signal subsystems. \nProficiencywith Microsoft-based development environments and Linux command-line tools, including GCC or Clang, Make, Bash, GDB, and Git. \nClear written and verbal communication, systematic debugging skills, and the ability to operateeffectively in a fast-moving environment with ambiguity. \nPreferred Qualifications \nMaster’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field. \nPython experience for test automation, debug tooling, data analysis, or lab workflows; hands-on experience with Jenkins and CI/CD infrastructure. \nFamiliarity with mixed-signal systems and analog signal paths, including ADC/DAC interfaces, sensor readout, transimpedance amplifiers, transmitdrivers, CTLE/DFE equalization, CDR/PLL circuits, or thermal control. \nExperience with retimeror gearbox firmware, SDK/API development, optical modules or pluggable optics, high-speed copper connectivity, Ethernet PHY subsystems, FEC, PMA, or signal-integrity analysis. \nExperience using oscilloscopes, BERTs, logic analyzers, and other lab equipment; familiarity with FPGA emulation, pre-silicon validation, RTOS, device drivers, coroutines, mentoring, or recruiting. \nSalary range is CAD $184,500 to CAD $205,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentivesand benefits. \nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.","description_format":"text","description_chars":6416,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Servers & Data Center Hardware"],"lifecycle":[{"event":"open","at":"2026-10-05T19:04:49Z"}],"visa":[{"country":"CA","licensed_sponsor":true,"evidence":"Positions approved through LMIA in 12 months: 1","filings_12m":1,"filings_prev_12m":4,"green_card_filings_12m":null,"median_offered_wage_usd":null,"route":"Global Talent Stream","cap_exempt":false,"checked_at":"2026-10-03T21:10:52+00:00","sources":["ESDC: employers issued a positive LMIA"],"filings_for_role_12m":0}],"liveness":{"score":63,"band":"ok","label":"Likely open","p_open":1,"p_active":0.632,"p_room":1,"age_days":8,"expected_fill_days":78,"reasons":["conf:3","stale_co","velocity","win:early","comp:brand"],"computed_at":"2026-10-14T06:34:16Z"},"pay":null,"html_url":"https://alion.io/job/astera-labs-principal-fwsw-engineer","json_url":"https://alion.io/job/astera-labs-principal-fwsw-engineer.json","meta":{"generated_at":"2026-10-14T14:16:33Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":17512,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-15T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":178069},"rest":"https://alion.io/mcp/rest/get_company?id=178069"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fastera-labs-principal-fwsw-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fastera-labs-principal-fwsw-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fastera-labs-principal-fwsw-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/astera-labs-principal-fwsw-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fastera-labs-principal-fwsw-engineer"}]}