{"id":2375829,"url":"https://alion.io/job/astera-labs-principal-mixed-analog-design-engineer","title":"Principal Mixed Analog Design Engineer","company":{"id":178069,"name":"Astera Labs","domain":"asteralabs.com","url":"https://alion.io/company/astera-labs-2","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"B","score":82,"open_postings":54,"ghost_share":0,"stale_share":0.537,"repost_share":0,"time_to_fill_p50_days":73,"computed_at":"2026-10-24T06:02:35Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Irvine, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":170000,"max":210000,"currency":"USD","period":"year","gross":null,"usd_annual":210000},"salary_estimate":null,"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Virtuoso","optional":false},{"name":"NVLink","optional":false}],"status":"live","first_seen_at":"2026-10-12T16:02:43Z","employer_posted_date":"2026-10-17","last_verified_at":"2026-10-24T22:24:34Z","board_verified":true,"closed_at":null,"days_open":12,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":12},"description":"Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\nAstera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\nRole Overview\nAstera Labs is redefining the connectivity that powers rack-scale AI infrastructure, and analog design is at the heart of it. As a Principal Analog Design Engineer, you will architect and design the high-performance analog and mixed-signal circuits that anchor our SerDes, PHY, and high-speed I/O - the silicon building blocks that move data at the speed AI demands. Your work directly shapes the performance, power, and reliability of products deployed in the world's most advanced data centers.\nThis is a high-impact, hands-on role at a hyper-growth company purpose-built for AI connectivity. You will own designs from concept through silicon bring-up, set the technical bar for the analog team, and mentor engineers as we scale. If you want your circuits to enable the next generation of AI compute, this is where that happens.\nKey Responsibilities\nAnalog & Mixed-Signal Design\nArchitect and design high-speed analog and mixed-signal circuits including PLLs, LDOs, references, high-speed SerDes building blocks, ADCs/DACs, and clocking.\n\nDrive circuit design from specification and architecture through schematic, layout supervision, and verification across PVT corners.\n\nDevelop robust designs in advanced FinFET process nodes with attention to power, area, and performance trade-offs.\n\nSilicon Execution & Validation\nLead silicon bring-up, characterization, and debug, partnering with validation and product engineering to root-cause and resolve issues.\n\nDefine and execute test plans to correlate silicon performance against design targets.\n\nTechnical Leadership\nSet analog design methodology, review standards, and best practices across the team.\n\nPartner cross-functionally with digital, physical design, systems, and architecture teams to deliver full-chip solutions.\n\nMentor and guide junior engineers, elevating the technical capability of the analog organization.\n\nBasic Qualifications\nMS or PhD in Electrical Engineering or a related field.\n\n8+ years of experience in analog and mixed-signal integrated circuit design.\n\nProven track record designing high-speed analog circuits such as PLLs, SerDes front-ends, data converters, references, or regulators in advanced CMOS/FinFET nodes.\n\nStrong understanding of physical-layer design principles, signal integrity, and high-speed I/O.\n\nProficiency with industry-standard design and simulation tools (e.g., Cadence Virtuoso, Spectre) and solid layout/parasitic-aware design skills.\n\nPreferred Qualifications\nExperience taking multiple analog/mixed-signal designs through full production tape-out and high-volume manufacturing.\n\nExpertise in high-speed serial link design (PCIe, Ethernet, UALink, UCIe) and associated PHY architectures.\n\nFamiliarity with silicon debug, ATE test development, and design-for-test techniques.\n\nExperience mentoring engineers and leading technical design reviews.\n\nExcellent communication skills and a collaborative, ownership-driven mindset.\n\nSalary range is $170,000 to $210,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.","description_format":"text","description_chars":4968,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Servers & Data Center Hardware"],"lifecycle":[{"event":"open","at":"2026-10-12T18:33:58Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 77 · green card filings: 7","filings_12m":77,"filings_prev_12m":50,"green_card_filings_12m":7,"median_offered_wage_usd":168155,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":0}],"liveness":{"score":63,"band":"ok","label":"Likely open","p_open":1,"p_active":0.632,"p_room":1,"age_days":11,"expected_fill_days":73,"reasons":["conf:3","stale_co","velocity","win:early","comp:brand"],"computed_at":"2026-10-24T06:02:35Z"},"pay":{"stated_usd_annual":210000,"is_top_pay":true},"html_url":"https://alion.io/job/astera-labs-principal-mixed-analog-design-engineer","json_url":"https://alion.io/job/astera-labs-principal-mixed-analog-design-engineer.json","meta":{"generated_at":"2026-10-24T22:35:00Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":33187,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-25T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":178069},"rest":"https://alion.io/mcp/rest/get_company?id=178069"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fastera-labs-principal-mixed-analog-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fastera-labs-principal-mixed-analog-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fastera-labs-principal-mixed-analog-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/astera-labs-principal-mixed-analog-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fastera-labs-principal-mixed-analog-design-engineer"}]}