{"id":3714099,"url":"https://alion.io/job/astera-labs-principal-pcspma-rtl-design-engineer","title":"Principal PCS/PMA RTL Design Engineer","company":{"id":178069,"name":"Astera Labs","domain":"asteralabs.com","url":"https://alion.io/company/astera-labs-2","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"B","score":81,"open_postings":48,"ghost_share":0,"stale_share":0.563,"repost_share":0,"time_to_fill_p50_days":77,"computed_at":"2026-11-10T06:52:35Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":185000,"max":240000,"currency":"USD","period":"year","gross":null,"usd_annual":240000},"salary_estimate":null,"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"NVLink","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"Cadence Genus","optional":true},{"name":"Cadence Tempus","optional":true},{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"Synopsys Design Compiler","optional":true},{"name":"Synopsys PrimeTime","optional":true}],"status":"live","first_seen_at":"2026-11-03T21:15:26Z","employer_posted_date":"2026-11-03","last_verified_at":"2026-11-11T03:50:41Z","board_verified":true,"closed_at":null,"days_open":7,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":7},"description":"Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\nPrincipal PCS/PMA RTL Design Engineer\nAstera Labs is seeking a Principal PCS/PMA RTL Design Engineer to join our San Jose design team, focused on the Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA) logic for high-speed interconnect standards such as Ethernet, PCIe, UCIe, and UALink. You will contribute to the architecture, implementation, integration, and verification of PCS/PMA digital logic for high-performance connectivity and networking ASICs.\nYou will work with experienced architects and design engineers to translate microarchitectural specifications into robust, synthesizable RTL. You will collaborate closely with SerDes/analog, verification, physical design, DFT, firmware, systems, and validation teams to deliver reliable designs through synthesis, timing closure, tapeout, and silicon validation.\nThis is a hands-on opportunity for an engineer who wants to build expertise in multi-protocol, multi-lane PHY digital design and contribute to products that enable next-generation AI and cloud infrastructure.\nKey responsibilities\nPCS/PMA RTL design and implementation\nDevelop synthesizable Verilog/SystemVerilog RTL for PCS and PMA digital blocks supporting Ethernet, PCIe, UCIe, UALink, and related protocols.\nImplement PCS functions such as line encoding/decoding (64b/66b, 128b/130b, 8b/10b), scrambling/descrambling, block and word alignment, lane deskew and reordering, gearboxes, elastic buffers/FIFOs, and rate adaptation.\nImplement forward error correction (e.g., RS-FEC/KP4, FEC framing, interleaving), plus the related error counters and status logic.\nImplement PMA digital interface logic, including SerDes datapath interfaces (PIPE, SerDes-facing parallel interfaces, UCIe PHY/raw-die interfaces), clock and data recovery (CDR) control interfaces, equalization and link-training control (e.g., PCIe LTSSM equalization, Ethernet auto-negotiation/link training), and calibration and adaptation control.\nDesign lane-level and multi-lane logic, including lane bonding, polarity and lane reversal, PRBS generation/checking, loopback modes, and BIST features.\nTranslate architectural and microarchitectural specifications into datapaths, control logic, state machines, register interfaces, and protocol logic.\nDesign reusable, configurable RTL modules that support multiple protocols, data rates, and lane configurations.\nIntegrate internal and third-party IP (including analog/mixed-signal PHY macros) while following established design and coding methodologies.\nParticipate in design reviews and contribute to improvements in RTL quality, reuse, latency, performance, power, and area.\nVerification and design quality\nCollaborate with design verification engineers to define functional requirements, test plans, and coverage goals, including protocol compliance (IEEE 802.3, PCI-SIG, UCIe, UALink specifications).\nDebug simulation failures using waveform analysis, assertions, regression results, and root-cause analysis.\nSupport lint, clock-domain crossing (CDC), reset-domain crossing (RDC), and RTL quality checks, with particular attention to multi-clock-domain PCS/PMA boundaries and asynchronous lane clocks.\nParticipate in UVM-based verification activities and help resolve functional and integration issues.\nSupport gate-level simulation and regression debug as required.\nSynthesis, timing, and implementation\nSupport logic synthesis, constraints development, and design implementation flows for high-speed, wide-datapath designs.\nPerform Static Timing Analysis (STA) and help identify and resolve setup, hold, clock, and interface timing issues, including at the SerDes and PHY boundaries.\nSupport timing closure, power optimization, and PPA trade-offs in collaboration with synthesis, timing, and physical-design teams.\nAssist with DFT integration, scan requirements, low-power intent (including per-lane power states), ECOs, and implementation signoff.\nReview reports and debug issues from Cadence and/or Synopsys digital design flows.\nSilicon and cross-functional collaboration\nSupport block-level and subsystem-level integration through tapeout milestones.\nCollaborate with SerDes/analog, physical design, DFT, firmware, systems, packaging, and validation teams.\nParticipate in silicon bring-up, link bring-up, interoperability and compliance testing, post-silicon debug, and failure analysis as opportunities arise.\nDocument design decisions, issues, and technical solutions clearly for cross-functional stakeholders.\nBasic qualifications\nBachelor's degree in Electrical Engineering, Computer Engineering, or a related field.\nMaster's degree is preferred.\n3+ years of relevant experience in digital ASIC, SoC, or RTL design, or equivalent academic and industry experience.\nHands-on experience with Verilog or SystemVerilog RTL development.\nUnderstanding of digital design fundamentals, including combinational and sequential logic, clocks, resets, state machines, datapaths, FIFOs, and interfaces.\nWorking knowledge of at least one high-speed serial protocol (Ethernet, PCIe, UCIe, UALink, CXL, or similar) at the PCS/PHY layer.\nExperience with RTL simulation, debugging, synthesis, and basic timing analysis.\nFamiliarity with ASIC design flows and collaboration across design and verification teams.\nStrong communication skills and the ability to work effectively in a collaborative, fast-paced environment.\nAbility and willingness to work onsite in San Jose, California.\nPreferred qualifications\nDirect experience designing PCS, PMA, or PHY digital logic for Ethernet (25G-224G per lane, 100G/200G/400G/800G/1.6T), PCIe (Gen4/5/6/7), UCIe, UALink, CXL, or similar standards.\nExperience with PAM4 signaling, FEC (RS-FEC/KP4, FLIT-mode FEC/CRC), lane deskew/alignment, link training, and equalization control.\nFamiliarity with the PIPE specification, 802.3 Clause 73/72/136/162-series, PCIe LTSSM, and UCIe link training and sideband.\nExperience with multi-lane, multi-rate SerDes digital datapaths and clocking architectures.\nFamiliarity with interconnect, networking, or data-center ASICs (retimers, switches, NICs, DPUs, SmartNICs, NoCs).\nFamiliarity with synthesis and implementation tools such as Cadence Genus/Innovus or Synopsys Design Compiler/ICC2.\nExperience with STA using tools such as Synopsys PrimeTime or Cadence Tempus.\nFamiliarity with lint, CDC/RDC, DFT, scan, GLS, LEC, UPF, or formal-verification flows.\nExperience with UVM, SystemVerilog Assertions, functional coverage, or verification-plan development.\nExperience with Python, Tcl, Perl, Shell, or other scripting languages for design and verification automation.\nExposure to advanced-node CMOS design (e.g., 5nm/3nm), tapeout, silicon bring-up, or post-silicon validation, including BER measurements and lab debug.\nExperience working with physical-design teams on floorplanning, congestion, timing, power, and implementation challenges.\nSalary range is $185,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.","description_format":"text","description_chars":8111,"description_truncated":false,"requirements":{"experience_years_min":3,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Servers & Data Center Hardware"],"lifecycle":[{"event":"open","at":"2026-11-04T00:17:50Z"}],"visa":[{"country":"US","licensed_sponsor":true,"adverts_offering_sponsorship_24m":0,"sanctioned_now":false,"evidence":"H-1B filings in 12 months: 77 · green card filings: 7","filings_12m":77,"filings_prev_12m":50,"green_card_filings_12m":7,"median_offered_wage_usd":168155,"route":null,"cap_exempt":false,"checked_at":"2026-11-10T11:34:35+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":54}],"liveness":{"score":63,"band":"ok","label":"Likely open","p_open":1,"p_active":0.632,"p_room":1,"age_days":6,"expected_fill_days":77,"reasons":["conf:5","stale_co","velocity","win:early","comp:brand"],"computed_at":"2026-11-10T06:52:35Z"},"pay":{"stated_usd_annual":240000,"is_top_pay":true},"html_url":"https://alion.io/job/astera-labs-principal-pcspma-rtl-design-engineer","json_url":"https://alion.io/job/astera-labs-principal-pcspma-rtl-design-engineer.json","meta":{"generated_at":"2026-11-11T04:03:09Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":3972,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-12T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.1,"usd":0.01,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":178069},"rest":"https://alion.io/mcp/rest/get_company?id=178069"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fastera-labs-principal-pcspma-rtl-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":2,"usd":0.2},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fastera-labs-principal-pcspma-rtl-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.1,"usd":0.01},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fastera-labs-principal-pcspma-rtl-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/astera-labs-principal-pcspma-rtl-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fastera-labs-principal-pcspma-rtl-design-engineer"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3714099}},{"tool":"search_jobs","arguments":{"company":"asteralabs.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3714099},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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