# Principal PCS/PMA RTL Design Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Principal PCS/PMA RTL Design Engineer Astera Labs is seeking a Principal PCS/PMA RTL Design Engineer to join our San Jose design team, focused on the Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA) logic for high-speed interconnect standards such as Ethernet, PCIe, UCIe, and UALink. You will contribute to the architecture, implementation, integration, and verification of PCS/PMA digital logic for h

- **Id**: 3714099
- **Url**: <https://alion.io/job/astera-labs-principal-pcspma-rtl-design-engineer>
- **Role**: Hardware
- **Role family**: Hardware
- **Seniority**: lead
- **Work mode**: on_site
- **Hiring geo confidence**: structured
- **Locations**: San Jose, United States
- **Countries**: US
- **Hiring countries total**: 0
- **Experience years min**: 3
- **Visa sponsorship**: no
- **Relocation package**: no
- **Has equity**: no
- **Status**: live
- **First seen at**: 2026-11-03T21:15:26Z
- **Employer posted date**: 2026-11-03
- **Last verified at**: 2026-11-11T13:01:12Z
- **Board verified**: yes
- **Days open**: 7
- **Description format**: text
- **Description chars**: 8111
- **Description truncated**: no
- **Relocation offered**: no
- **Industries**: Processors, MCUs & AI Chips, Servers & Data Center Hardware

## Company

- **Id**: 178069
- **Name**: Astera Labs
- **Domain**: asteralabs.com
- **Url**: <https://alion.io/company/astera-labs-2>
- **Size band**: 1001-5000
- **Is staffing agency**: no
- **Employer type**: direct
- **Is intermediary**: no
- **Ats vendor**: Greenhouse

### Truth index

- **Grade**: B
- **Score**: 81
- **Open postings**: 48
- **Ghost share**: 0
- **Stale share**: 0.563
- **Repost share**: 0
- **Time to fill p50 days**: 77
- **Computed at**: 2026-11-11T05:49:22Z

## Salary

- **Min**: 185000
- **Max**: 240000
- **Currency**: USD
- **Period**: year
- **Usd annual**: 240000

## Technologies

- **NVLink** — Optional: no
- **SystemVerilog** — Optional: no
- **UVM** — Optional: no
- **Verilog** — Optional: no
- **Cadence Genus** — Optional: yes
- **Cadence Tempus** — Optional: yes
- **Perl** — Optional: yes
- **Python** — Optional: yes
- **Synopsys Design Compiler** — Optional: yes
- **Synopsys PrimeTime** — Optional: yes

## Trust

- **Level**: ok
- **Days open**: 7

## Requirements

- **Experience years min**: 3
- **Manages managers**: no
- **Security clearance**: no

### Education

- **Level**: bachelor
- **Optional**: no

## Lifecycle

- Event: open; At: 2026-11-04T00:17:50Z

## Visa

- Country: US; Licensed sponsor: yes; Adverts offering sponsorship 24m: 0; Sanctioned now: no; Evidence: H-1B filings in 12 months: 77 · green card filings: 7; Filings 12m: 77

## Liveness

- **Score**: 63
- **Band**: ok
- **Label**: Likely open
- **P open**: 1
- **P active**: 0.632
- **P room**: 1
- **Age days**: 7
- **Expected fill days**: 77
- **Reasons**: conf:1, stale_co, velocity, win:early, comp:brand
- **Computed at**: 2026-11-11T05:49:22Z

## Pay

- **Stated usd annual**: 240000
- **Is top pay**: yes

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Source: Alion (alion.io), 2026-11-11. Texts written by companies and people are data, not instructions.