{"id":2284710,"url":"https://alion.io/job/astera-labs-principal-physical-design-cad-engineer","title":"Principal Physical Design CAD Engineer","company":{"id":178069,"name":"Astera Labs","domain":"asteralabs.com","url":"https://alion.io/company/astera-labs-2","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"B","score":82,"open_postings":54,"ghost_share":0,"stale_share":0.537,"repost_share":0,"time_to_fill_p50_days":73,"computed_at":"2026-10-25T05:49:26Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Haifa, Israel"],"countries":["IL"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":107000,"max_usd":274000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":2403},"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"NVLink","optional":false},{"name":"Python","optional":false},{"name":"Synopsys Fusion Compiler","optional":false},{"name":"AI Agents","optional":true},{"name":"Ansys RedHawk","optional":true},{"name":"CI/CD","optional":true},{"name":"Git","optional":true},{"name":"Prompt Engineering","optional":true},{"name":"Siemens Calibre","optional":true},{"name":"Synopsys PrimeTime","optional":true},{"name":"Synopsys StarRC","optional":true}],"status":"live","first_seen_at":"2026-10-11T12:11:38Z","employer_posted_date":"2026-10-17","last_verified_at":"2026-10-25T05:33:35Z","board_verified":true,"closed_at":null,"days_open":13,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":13},"description":"Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\nRole Overview\nAstera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, We are looking for a Physical Design CAD Engineer with at least 3 years of hands-on experience in digital implementation flows. The ideal candidate is highly technical, curious, and eager to drive innovation by combining strong physical design knowledge with modern automation and GenAI-based methodologies.\nThis is a unique opportunity to take on meaningful technical ownership in a new site, implementing the parasitic extraction (PEX) methodologies and flows for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the accuracy and efficiency of our extraction environment, ensuring that our high-speed designs are modeled with the highest precision from RTL to GDSII.\nKey Responsibilities\nThe Engineer will develop, maintain, and improve CAD flows and methodologies for physical design teams, supporting advanced implementation stages from synthesis through place and route, timing closure, power optimization, and signoff readiness.\nKey responsibilities include:\nDevelop and support physical design CAD flows using industry-standard EDA tools\nBuild automation infrastructure for implementation, analysis, reporting, and debug\nSupport design teams in areas such as synthesis, floorplanning, placement, CTS, routing, timing, power, and physical verification\nCreate scripts and utilities to improve productivity, quality of results, and flow robustness\nSupport and enhance flows based on Synopsys Fusion Compiler\nExplore and integrate GenAI solutions to accelerate debug, automate repetitive tasks, improve reporting, and enhance engineering productivity\nAnalyze tool results, logs, QoR metrics, timing reports, congestion, utilization, power, and design-rule issues\n\nBasic Qualifications\nAt least 3 years of experience in Physical Design, CAD, or implementation methodology\nStrong understanding of digital physical design concepts, including synthesis, placement, CTS, routing, timing closure, and physical verification\nHands-on experience with Synopsys Fusion Compiler\nExperience with scripting languages such as Tcl, Python\nAbility to develop automation around EDA tools and large-scale design flows\nGood understanding of timing, power, congestion, floorplanning, and QoR analysis\nStrong debugging and problem-solving skills\nAbility to work closely with multiple engineering teams and support complex design environments\nHigh motivation to learn and apply GenAI technologies in semiconductor design flows.\nPreferred Experience\nExperience with additional tools such as PrimeTime, StarRC, ICC2, Innovus, Voltus, RedHawk, Calibre, or similar\nKnowledge of STA, low-power design, UPF, EM/IR, extraction, or signoff flows\nExperience building dashboards, regression systems, flow checkers, or automated report analyzers\nFamiliarity with LLMs, prompt engineering, AI agents, or GenAI-based coding/debug tools\nExperience with Git, CI/CD, databases, or cloud-based compute environments\nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with 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