{"id":2320151,"url":"https://alion.io/job/astera-labs-principal-physical-design-engineer-3","title":"Principal Physical Design Engineer","company":{"id":178069,"name":"Astera Labs","domain":"asteralabs.com","url":"https://alion.io/company/astera-labs-2","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"B","score":81,"open_postings":54,"ghost_share":0,"stale_share":0.574,"repost_share":0,"time_to_fill_p50_days":73,"computed_at":"2026-10-22T06:10:10Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Ahmedabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":24000,"max_usd":54000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":741},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"NVLink","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-10-12T05:29:15Z","employer_posted_date":"2026-10-17","last_verified_at":"2026-10-22T05:14:10Z","board_verified":true,"closed_at":null,"days_open":10,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":10},"description":"Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\nPhysical Design \nAstera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com. \nBasic qualifications:\nStrong academic and technical background in electrical engineering. A Bachelor’s degree in EE / Computer is required, and a Master’s degree is preferred.\n≥8 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.\nProfessional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision. \nEntrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!\nRequired experience:\nHands-on and thorough knowledge of synthesis, place and route, CTS, extraction timing analysis/STA, Physical Verification and other backend tools and methodologies for technologies 16nm or less, preferably 7nm or less.\nProven expertise in synthesis, timing closure and formal verification (equivalence) at the block and full-chip level.\nFull chip or block level ownership from architecture to GDSII, driving multiple complex designs to production.\nExperience with Cadence and/or Synopsys physical design tools/flows.\nFamiliarity and working knowledge of System Verilog/Verilog.\nExperience with DFT tools and techniques.\nExperience in working with IP vendors for both RTL and hard-mac blocks.\nGood scripting skills in python or Perl\nPreferred :\nGood knowledge of design for test (DFT), stuck-at and transition scan test insertion.\nFamiliarity with DFT test coverage and debug.\nFamiliarity with ECO methodologies and tools.\nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.","description_format":"text","description_chars":3289,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Servers & Data Center Hardware"],"lifecycle":[{"event":"open","at":"2026-10-12T06:01:44Z"}],"visa":[],"liveness":{"score":63,"band":"ok","label":"Likely open","p_open":1,"p_active":0.632,"p_room":1,"age_days":10,"expected_fill_days":73,"reasons":["conf:0","stale_co","velocity","win:early","comp:brand"],"computed_at":"2026-10-22T06:10:10Z"},"pay":null,"html_url":"https://alion.io/job/astera-labs-principal-physical-design-engineer-3","json_url":"https://alion.io/job/astera-labs-principal-physical-design-engineer-3.json","meta":{"generated_at":"2026-10-22T07:33:39Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":3226,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-23T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":178069},"rest":"https://alion.io/mcp/rest/get_company?id=178069"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fastera-labs-principal-physical-design-engineer-3"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fastera-labs-principal-physical-design-engineer-3"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fastera-labs-principal-physical-design-engineer-3"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/astera-labs-principal-physical-design-engineer-3\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fastera-labs-principal-physical-design-engineer-3"}]}