{"id":1470074,"url":"https://alion.io/job/astera-labs-principal-verification-engineer","title":"Principal Verification Engineer","company":{"id":178069,"name":"Astera Labs","domain":"asteralabs.com","url":"https://alion.io/company/astera-labs-2","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"B","score":83,"open_postings":59,"ghost_share":0,"stale_share":0.492,"repost_share":0,"time_to_fill_p50_days":81,"computed_at":"2026-10-01T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":185000,"max":230000,"currency":"USD","period":"year","gross":null,"usd_annual":230000},"salary_estimate":null,"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"NVLink","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"InfiniBand","optional":true}],"status":"live","first_seen_at":"2026-09-29T13:01:30Z","employer_posted_date":"2026-09-29","last_verified_at":"2026-10-01T17:28:36Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\nAstera Labs is seeking a Principal Design Verification Engineer with strong problem-solving abilities and a passion for developing robust verification methodologies for complex ASICs. The ideal candidate will have a solid background in SystemVerilog and experience with C/C++, Python, or similar scripting languages. This role involves full lifecycle verification-from planning and test development to debugging and coverage closure-contributing to the success of cutting-edge SoC designs.\nKey Responsibilities\nLead the functional verification of advanced ASICs, including test planning, development, execution, and coverage analysis.\nCollaborate closely with software and system validation teams to create and execute test plans on emulation platforms.\nApply both directed and constrained-random verification techniques using SystemVerilog/UVM and other relevant tools.\nDebug test failures, analyze coverage results, and close functional coverage gaps to ensure comprehensive verification.\nWork with RTL designers to troubleshoot and resolve design issues.\nDrive verification strategy and methodology for SoCs in server and networking applications.\nRequired Qualifications\nBachelor’s degree in Electrical Engineering (Master’s preferred).\n8+ years of experience in SoC verification, particularly for server and networking applications.\nExpertise in SystemVerilog/UVM and hands-on experience across the full verification lifecycle.\nProficiency with industry-standard simulators, version control, and regression systems.\nStrong debugging and coverage analysis skills.\nExperience developing and executing test sequences, generating stimuli, and identifying verification holes.\nFamiliarity with verification of switching architectures, including packet processing and forwarding engines.\nExcellent communication skills and ability to work independently with minimal supervision.\nPreferred Qualifications\nExperience with third-party Verification IP for protocols such as PCIe, Ethernet, and InfiniBand.\nBackground in Network-on-Chip (NoC) architectures for smart NICs and AI accelerators.\nKnowledge of Ethernet/PCIe switching and central buffer architectures.\nExperience with emulation platforms and hardware-software co-verification\nSalary range is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.","description_format":"text","description_chars":3474,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Servers & Data Center Hardware"],"lifecycle":[{"event":"open","at":"2026-09-29T15:49:08Z"}],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":1,"expected_fill_days":81,"reasons":["conf:11","velocity","win:early","comp:brand"],"computed_at":"2026-10-01T05:45:00Z"},"pay":{"stated_usd_annual":230000,"is_top_pay":true},"html_url":"https://alion.io/job/astera-labs-principal-verification-engineer","json_url":"https://alion.io/job/astera-labs-principal-verification-engineer.json","meta":{"generated_at":"2026-10-02T00:53:09Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":938,"day_limit":5000,"remaining_today":4062,"minute_limit":60,"resets_at":"2026-10-03T00:00:00Z"}}}