{"id":1424344,"url":"https://alion.io/job/astera-labs-senior-design-verification-engineer-3","title":"Senior Design Verification Engineer","company":{"id":178069,"name":"Astera Labs","domain":"asteralabs.com","url":"https://alion.io/company/astera-labs-2","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"B","score":82,"open_postings":53,"ghost_share":0,"stale_share":0.509,"repost_share":0,"time_to_fill_p50_days":78,"computed_at":"2026-10-12T06:55:09Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":148500,"max":165000,"currency":"USD","period":"year","gross":null,"usd_annual":165000},"salary_estimate":null,"experience_years_min":2,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"NVLink","optional":false},{"name":"UVM","optional":false},{"name":"Formal Verification","optional":true},{"name":"Perl","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-09-28T21:15:04Z","employer_posted_date":"2026-09-28","last_verified_at":"2026-10-12T18:33:58Z","board_verified":true,"closed_at":null,"days_open":13,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":13},"description":"Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\nRole Overview \nAs a Senior Design Verification Engineer, you will help define and deliver robust verification for next-generation connectivity silicon that enables rack-scale AI infrastructure. You will partner closely with RTL, architecture, firmware, and post-silicon teams to build verification strategies that prove complex switching behavior across high-bandwidth protocols and demanding system environments. \nThis role offers the opportunity to own meaningful verification challenges within CCE2, from planning and testbench architecture through coverage closure and silicon learning. You will contribute to Astera Labs’ hyper-growth mission by helping deliver highly reliablePCIe and UALinkconnectivity products that keep AI accelerators, memory, and compute resources operatingat scale. \nKey Responsibilities \nVerification Strategy and Planning \nDevelop block- and subsystem-level verification plans from specifications, architecture, and design requirements. \nDefine test scenarios, coverage models, checkers, assertions, and scoreboards for complex switching functionality. \nReview designs and verification plans with architecture and RTL teams to identifycorner cases early. \nEnvironment Development and Execution \nBuild and enhance reusable UVM-based SystemVerilogtestbenches, agents, sequences, monitors, and reference models. \nCreate directed, constrained-random, and power-on-reset scenarios spanning PCIe Gen 6/Gen 7, UALink, and UCI behavior. \nDebug simulation failures using waveform analysis, logs, assertions, and cross-functional collaboration. \nCoverage, Quality, and Silicon Readiness \nDrive functional and code coverage analysis, identifyverification gaps, and close coverage to agreed milestones. \nDevelop regression strategies and automation to improve test quality, turnaround time, and failure triage. \nPartner with design and post-silicon teams on issueisolation, root-cause analysis, and silicon bring-up readiness. \nBasic Qualifications \nBachelor’s degree in Electrical Engineering, Computer Engineering, or a relatedtechnical field. \n2-5 years of experience in design verification for complex ASICs or SoCs. \nHands-on experience with SystemVerilogand UVM-based verification environments. \nExperience developing verification plans, testbenches, assertions, scoreboards, and functional coverage models. \nFamiliarity with simulation, waveform-debug, regression, and coverage tools. \nStrong debugging, communication, and collaboration skills in a fast-paced product development environment. \nPreferred Qualifications \nMaster’s degree in Electrical Engineering, Computer Engineering, or a relatedfield. \nExperience verifying PCIe, UALink, UCI, or other high-speed connectivity and switching protocols. \nKnowledge of protocol checkers, formal verification, emulation, or hardware acceleration methodologies. \nExperience with Python, Perl, or Tclfor verificationautomation and regression infrastructure. \nUnderstanding of AI or data-center system architectures, including accelerator, memory, and fabric connectivity. \nSalary range is $148,500 to $165,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentivesand benefits.\nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.","description_format":"text","description_chars":4287,"description_truncated":false,"requirements":{"experience_years_min":2,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Servers & Data Center Hardware"],"lifecycle":[{"event":"open","at":"2026-09-28T23:17:20Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 77 · green card filings: 7","filings_12m":77,"filings_prev_12m":50,"green_card_filings_12m":7,"median_offered_wage_usd":168155,"route":null,"cap_exempt":false,"checked_at":"2026-10-03T21:08:04+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":54}],"liveness":{"score":63,"band":"ok","label":"Likely open","p_open":1,"p_active":0.632,"p_room":1,"age_days":13,"expected_fill_days":78,"reasons":["conf:0","stale_co","velocity","win:early","comp:brand"],"computed_at":"2026-10-12T06:55:09Z"},"pay":{"stated_usd_annual":165000,"is_top_pay":false},"html_url":"https://alion.io/job/astera-labs-senior-design-verification-engineer-3","json_url":"https://alion.io/job/astera-labs-senior-design-verification-engineer-3.json","meta":{"generated_at":"2026-10-12T20:41:39Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":33600,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-13T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":178069},"rest":"https://alion.io/mcp/rest/get_company?id=178069"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fastera-labs-senior-design-verification-engineer-3"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fastera-labs-senior-design-verification-engineer-3"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fastera-labs-senior-design-verification-engineer-3"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/astera-labs-senior-design-verification-engineer-3\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fastera-labs-senior-design-verification-engineer-3"}]}