{"id":690581,"url":"https://alion.io/job/astera-labs-senior-digital-design-engineer","title":"Senior Digital Design Engineer","company":{"id":178069,"name":"Astera Labs","domain":"asteralabs.com","url":"https://alion.io/company/astera-labs-2","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"B","score":82,"open_postings":50,"ghost_share":0,"stale_share":0.52,"repost_share":0,"time_to_fill_p50_days":77,"computed_at":"2026-11-03T05:54:40Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"explicit","locations":["Toronto, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":89000,"max_usd":156000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":74},"experience_years_min":2,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"NVLink","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"CI/CD","optional":true}],"status":"live","first_seen_at":"2026-09-10T22:21:14Z","employer_posted_date":"2026-10-17","last_verified_at":"2026-11-03T18:40:46Z","board_verified":true,"closed_at":null,"days_open":54,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":54},"description":"Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\nRole Overview \nAs a Senior Digital Design Engineer, you will design and integrate high-performance connectivity silicon for the next generation of AI infrastructure. You will contribute across architecture, micro-architecture, RTL implementation, synthesis, timing closure, and IP integration for PCIe and Ethernet controllers, bridges, switches, and related SerDes interfaces. \nYou will work with cross-functional teams to turn complex connectivity requirements into robust, production-ready designs. Your work will span block-level and full-chip development at advanced process nodes and help enable reliable, high-bandwidth connections among CPUs, GPUs, memory, storage, and networking devices in rack-scale AI systems. You will help improve product quality, accelerate time to market, and strengthen customer confidence in every release. \nKey Responsibilities \nDigital Architecture and RTL Implementation \nDevelop micro-architecture and implement synthesizable RTL for high-performance PCIe or Ethernet controllers, bridges, switches, and SerDes-related IP. \nTranslate architecture and protocol requirements into scalable designs using SystemVerilog and Verilog. \nOwn block-level and full-chip design deliverables from specification through implementation and GDS handoff. \nContribute to designs at advanced process nodes of 16 nm or smaller, including PCIe Gen 6/7, UALink, or UCI-based connectivity where applicable. \nIntegration, Timing, and Design Quality \nIntegrate controller, SerDes, processor, peripheral, and other IP while partnering with RTL, physical design, DFT, verification, and firmware teams. \nDrive synthesis, timing analysis, timing closure, clock-domain crossing, lint, and design-quality reviews. \nSupport gate-level simulation, emulation, and pre-silicon and post-silicon design implementation activities. \nContribute to top-level integration, floor-planning discussions, PAD planning, and DFT implementation. \n Cross-Functional Execution and Debug \nCollaborate with verification and system teams to assess verification completeness, debug design issues, and close implementation gaps. \nPartner with firmware and embedded software teams to define and validate hardware-software interfaces. \nUse Synopsys and Cadence design and analysis tools, along with Python or Perl scripting, to improve design productivity and automation. \nCommunicate technical status, risks, and tradeoffs clearly while managing multiple priorities with appropriate ownership and urgency. \nBasic Qualifications \nBachelor’s degree in Electrical Engineering, Electronics Engineering, or a related field. \n2 - 5 years of experience in digital design and implementation for complex SoC or silicon products. \nHands-on experience developing RTL in SystemVerilog or Verilog, including synthesis and timing closure. \nExperience with PCIe or Ethernet controller, bridge, switch, PCS, PHY, or SerDes design and IP integration. \nExperience with front-end design, gate-level simulation, clock-domain crossing, lint, or related design-quality methodologies. \nExperience using Python or Perl to automate design, integration, or analysis workflows. \nAbility to collaborate effectively across design, verification, physical design, DFT, firmware, and system teams. \nAuthorized to work in Canada. \nPreferred Qualifications \nExperience with PCIe or Ethernet SerDes controller or IP-level design, including PCIe Gen 6/7, UALink, or UCI. \nExperience with block-level and full-chip implementation at advanced process nodes of 16 nm or smaller. \nKnowledge of PAD design, DFT, floor planning, and top-level integration. \nExperience developing NIC, switch, storage, or other high-performance connectivity products with embedded firmware interaction. \nFamiliarity with continuous integration and continuous delivery workflows for design and verification. \nExperience with FPGA-based prototyping, emulation, or post-silicon debug. \nSalary range is $139,500 to $155,000 CAD depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits. \nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.","description_format":"text","description_chars":5154,"description_truncated":false,"requirements":{"experience_years_min":2,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"Canada","iso":"CA","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Servers & Data Center Hardware"],"lifecycle":[{"event":"open","at":"2026-09-11T00:57:05Z"}],"visa":[{"country":"CA","licensed_sponsor":true,"evidence":"Positions approved through LMIA in 12 months: 1","filings_12m":1,"filings_prev_12m":4,"green_card_filings_12m":null,"median_offered_wage_usd":null,"route":"Global Talent Stream","cap_exempt":false,"checked_at":"2026-10-03T21:10:52+00:00","sources":["ESDC: employers issued a positive LMIA"],"filings_for_role_12m":1}],"liveness":{"score":55,"band":"ok","label":"Likely open","p_open":1,"p_active":0.61,"p_room":0.9,"age_days":53,"expected_fill_days":77,"reasons":["conf:1","stale_co","velocity","win:mid","comp:brand"],"computed_at":"2026-11-03T05:54:40Z"},"pay":null,"html_url":"https://alion.io/job/astera-labs-senior-digital-design-engineer","json_url":"https://alion.io/job/astera-labs-senior-digital-design-engineer.json","meta":{"generated_at":"2026-11-03T23:23:47Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":2063,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-04T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":178069},"rest":"https://alion.io/mcp/rest/get_company?id=178069"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fastera-labs-senior-digital-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fastera-labs-senior-digital-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fastera-labs-senior-digital-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/astera-labs-senior-digital-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fastera-labs-senior-digital-design-engineer"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":690581}},{"tool":"search_jobs","arguments":{"company":"asteralabs.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":690581},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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