{"id":462396,"url":"https://alion.io/job/astera-labs-senior-principal-digital-design-engineer","title":"Senior Principal Digital Design Engineer","company":{"id":178069,"name":"Astera Labs","domain":"asteralabs.com","url":"https://alion.io/company/astera-labs-2","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"B","score":81,"open_postings":51,"ghost_share":0,"stale_share":0.549,"repost_share":0,"time_to_fill_p50_days":73,"computed_at":"2026-10-31T05:58:55Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":205000,"max":255000,"currency":"USD","period":"year","gross":null,"usd_annual":255000},"salary_estimate":null,"experience_years_min":12,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"NVLink","optional":false}],"status":"live","first_seen_at":"2026-03-12T19:00:10Z","employer_posted_date":"2026-10-17","last_verified_at":"2026-10-31T15:47:24Z","board_verified":true,"closed_at":null,"days_open":232,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":232},"description":"Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\nRole Overview\nAstera Labs is seeking a Senior Principal Digital Design Engineer to drive the architecture and implementation of next-generation digital designs powering AI infrastructure connectivity. This is a high-impact technical leadership role where you'll define micro-architecture strategies for better power, performance and area tradeoff, own complex chip-level design decisions, and guide multiple blocks from concept through silicon bring-up for industry-leading products supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols.\nAs a senior technical leader, you'll shape design methodologies, mentor engineering teams, and collaborate cross-functionally with verification, physical design, DFT, and post-silicon teams to deliver high-performance, production-quality silicon. You'll also influence roadmap decisions and drive design excellence across the organization, ensuring Astera Labs continues to set the standard for AI connectivity solutions.\nKey Responsibilities\nArchitecture & Technical Leadership\nDefine and drive micro-architecture for complex digital blocks and subsystems across multiple product lines\nEstablish architectural standards and best practices that scale across the design organization\nProvide technical guidance and decision-making on critical design trade-offs impacting performance, power, and area\n Design Execution & Ownership\nLead RTL implementation of complex designs from architecture definition through GDS and silicon bring-up\nDrive timing constraints and closure strategies and implement robust Design-for-Test (DFT) methodologies\nOwn accountability for design quality, schedule, and successful production delivery\nCross-Functional Collaboration\nPartner with verification teams to develop comprehensive test plans, achieve coverage closure, and debug complex issues\nCollaborate with physical design, DFT, and post-silicon teams to ensure seamless integration and bring-up\nWork with firmware and software teams to optimize hardware-software interfaces\nMentorship & Process Excellence\nMentor and develop junior and senior engineers, elevating team technical capabilities\nDrive continuous improvement of silicon development processes, CAD automation, and design infrastructure\nContribute to organizational knowledge sharing and technical reviews\nBasic Qualifications\nBachelor's degree in Electrical Engineering or equivalent\n12+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets\nDemonstrated expertise in architecture definition, micro-architecture development, RTL coding, synthesis, and timing closure\nDeep knowledge of at least one high-speed protocol: PCIe, CXL, Ethernet, DDR, or similar\nProduction experience with advanced CMOS nodes (≤7nm)\nProficiency with Cadence and/or Synopsys digital design flows\nTrack record of delivering multiple high-performance designs to production\nPreferred Qualifications\nMaster's degree in Electrical Engineering or related field\nExperience with multiple high-speed protocols (PCIe Gen 5/6, CXL, UALink, Ethernet, DDR4/DDR5)\nHands-on collaboration with embedded firmware teams and familiarity with RISC-V or Arm subsystems\nProven contributions to design methodology, CAD automation, or infrastructure improvements\nExperience leading technical teams or driving cross-functional initiatives in data center environments\nSalary range is $205,000 to $255,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.","description_format":"text","description_chars":4629,"description_truncated":false,"requirements":{"experience_years_min":12,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Servers & Data Center Hardware"],"lifecycle":[{"event":"open","at":"2026-09-06T11:26:14Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 77 · green card filings: 7","filings_12m":77,"filings_prev_12m":50,"green_card_filings_12m":7,"median_offered_wage_usd":168155,"route":null,"cap_exempt":false,"checked_at":"2026-10-29T16:27:21+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":0}],"liveness":{"score":11,"band":"cold","label":"Long shot","p_open":1,"p_active":0.408,"p_room":0.28,"age_days":232,"expected_fill_days":73,"reasons":["conf:1","stale_co","velocity","win:tail","crowd:brand"],"computed_at":"2026-10-31T05:58:55Z"},"pay":{"stated_usd_annual":255000,"is_top_pay":true},"html_url":"https://alion.io/job/astera-labs-senior-principal-digital-design-engineer","json_url":"https://alion.io/job/astera-labs-senior-principal-digital-design-engineer.json","meta":{"generated_at":"2026-10-31T17:59:03Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":28146,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-01T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":178069},"rest":"https://alion.io/mcp/rest/get_company?id=178069"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fastera-labs-senior-principal-digital-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fastera-labs-senior-principal-digital-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fastera-labs-senior-principal-digital-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/astera-labs-senior-principal-digital-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fastera-labs-senior-principal-digital-design-engineer"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":462396}},{"tool":"search_jobs","arguments":{"company":"asteralabs.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":462396},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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