{"id":3587582,"url":"https://alion.io/job/astera-labs-senior-staff-physical-design-engineer-2","title":"Senior/ Staff Physical Design Engineer","company":{"id":178069,"name":"Astera Labs","domain":"asteralabs.com","url":"https://alion.io/company/astera-labs-2","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"B","score":82,"open_postings":50,"ghost_share":0,"stale_share":0.52,"repost_share":0,"time_to_fill_p50_days":78,"computed_at":"2026-11-05T05:54:30Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Tel Aviv, Israel"],"countries":["IL"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":116000,"max_usd":269000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":1702},"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"NVLink","optional":false},{"name":"Python","optional":false},{"name":"Cadence Innovus","optional":true},{"name":"Synopsys Fusion Compiler","optional":true}],"status":"live","first_seen_at":"2026-11-01T10:46:49Z","employer_posted_date":"2026-11-01","last_verified_at":"2026-11-05T20:47:30Z","board_verified":true,"closed_at":null,"days_open":4,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":4},"description":"Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\nRole Overview\nAstera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.\nAs a Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow-you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.\nKey Responsibilities\nPhysical Implementation & Execution\nBe part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards\nTake full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS)\nOwn macro-level implementation with deep hands-on experience in floorplanning and complex routing\n\nSignoff & Design Integrity\nDrive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)\nEnsure first-pass silicon success through rigorous signoff flows and analysis\nApply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness\n\nMethodology Development & Cross-Functional Collaboration\nParticipate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation\nWork closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity\nLeverage scripting and automation to make engineering environment faster and more robust\n\nBasic Qualifications\nBachelor's degree in Electrical Engineering or related technical field\n3+ years of hands-on experience in Physical Design at semiconductor companies\nProven expertise in the full RTL2GDS flow with deep hands-on experience in macro-level implementation, floorplanning, and complex routing\nExperience working with advanced process technologies (7nm and below)\nSolid experience with signoff tools and flows including STA, Logic Equivalence Checking (LEC), DRC, and EMIR analysis\nProficiency in TCL or Python scripting to drive EDA tool flows and automate repetitive tasks\nPreferred Qualifications\nExperience with full-chip level implementation and integration\nKnowledge of Power and Noise analysis (SI/PI) to optimize high-performance silicon\nFamiliarity with Design-for-Test (DFT) requirements and their impact on physical layout\nExperience with industry-standard EDA tools (Synopsys Fusion Compiler/ICC2, Cadence Innovus)\nBackground in high-speed interface designs or connectivity protocols\nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with 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