{"id":1916341,"url":"https://alion.io/job/astera-labs-silicon-design-architect","title":"Silicon Design Architect","company":{"id":178069,"name":"Astera Labs","domain":"asteralabs.com","url":"https://alion.io/company/astera-labs-2","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"B","score":82,"open_postings":53,"ghost_share":0,"stale_share":0.509,"repost_share":0,"time_to_fill_p50_days":78,"computed_at":"2026-10-12T06:55:09Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":37000,"max_usd":76000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":539},"experience_years_min":20,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"NVLink","optional":false}],"status":"live","first_seen_at":"2026-09-22T09:46:03Z","employer_posted_date":"2026-10-05","last_verified_at":"2026-10-13T04:47:19Z","board_verified":true,"closed_at":null,"days_open":20,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":20},"description":"Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\nSilicon Digital Architect - IP / Subsystem\n\nExperience-20+ years\nJob Summary\nWe are looking for an experienced IP/Subsystem Architect to define the architecture and technical direction of complex semiconductor IPs and subsystems. The candidate will own architecture definition from requirements through implementation, working closely with SoC, RTL, verification, physical design, firmware, and system teams.\nKey Responsibilities\nDefine architecture for complex IP blocks and SoC subsystems based on product and system requirements.\nTranslate system requirements into architecture, specifications, interfaces, and performance targets.\nDefine microarchitecture, data paths, control paths, interfaces, clocking, reset, power, and error-handling mechanisms.\nEvaluate architectural trade-offs across performance, power, area, latency, bandwidth, scalability, and complexity.\nDefine interfaces and protocols such as PCIe, UALink, AXI, APB, CHI, or other high-speed/interconnect protocols.\nDevelop architecture specifications, block diagrams, interface specifications, and technical documentation.\nWork closely with RTL, verification, physical design, DFT, firmware, and system architecture teams.\nIdentify architectural risks and drive resolution of complex technical issues.\nReview RTL and verification strategies to ensure implementation aligns with architectural intent.\nProvide technical leadership and mentorship to senior/principal engineers.\nDrive architecture reviews and communicate technical decisions to engineering leadership.\nRequired Skills\nStrong background in IP architecture and microarchitecture\nBackground in ASIC/SoC architecture and microarchitecture is a big plus.\nStrong understanding of digital design, computer architecture, memory systems, interconnects, and SoC design.\nExperience with high-speed interfaces and/or coherent interconnects.\nStrong understanding of performance modeling, bandwidth, latency, and system-level trade-offs.\nExcellent technical communication and problem-solving skills.\nPreferred\nExperience with PCIe, UALink, CXL, Ethernet, CCIX, CHI, or similar technologies.\nExperience with AI/accelerator, networking, compute, or high-performance SoC architectures.\nExperience taking IP/subsystems from architecture through silicon production.\nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.","description_format":"text","description_chars":3359,"description_truncated":false,"requirements":{"experience_years_min":20,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Servers & Data Center Hardware"],"lifecycle":[{"event":"open","at":"2026-10-05T16:21:24Z"}],"visa":[],"liveness":{"score":63,"band":"ok","label":"Likely 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