{"id":462451,"url":"https://alion.io/job/astera-labs-sr-principal-program-manager-asic-design","title":"Sr. Principal Program Manager, ASIC Design","company":{"id":178069,"name":"Astera Labs","domain":"asteralabs.com","url":"https://alion.io/company/astera-labs-2","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"B","score":80,"open_postings":53,"ghost_share":0,"stale_share":0.585,"repost_share":0,"time_to_fill_p50_days":78,"computed_at":"2026-10-13T05:45:00Z"}},"role":"Management","role_family":"Management","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Toronto, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":67000,"max_usd":159000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":209},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"NVLink","optional":false}],"status":"live","first_seen_at":"2026-06-25T01:07:52Z","employer_posted_date":"2026-09-23","last_verified_at":"2026-10-13T15:49:24Z","board_verified":true,"closed_at":null,"days_open":110,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":110},"description":"Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\nRole Overview\nAs a Sr. Principal Program Manager, ASIC Design at Astera Labs, you will own the cross-functional execution framework for advanced ASIC programs from early planning through tapeout. You will drive milestones, dependencies, execution reviews, decision-making forums, risk management, and tapeout readiness across multiple engineering teams.\nYou will partner closely with architecture, RTL design, functional verification, emulation, DFT, synthesis, physical design, CAD, IP, product management, engineering leadership, and external partners.\nThis is a high-impact role for a technical program leader who can operate in a fast-moving environment, manage ambiguity, drive accountability, and establish scalable execution practices across complex silicon development programs.\nKey Responsibilities\nProgram Execution & Planning\nLead pre-silicon execution of complex ASIC and subsystem programs from concept through tapeout.\nOwn program plans, schedules, milestones, dependencies, risk registers, dashboards, and executive-level status reporting.\nDrive pre-silicon and NPD phase-gate execution from kickoff through final GDS handoff, ensuring cross-functional readiness across architecture, RTL, verification, DFT, physical design, signoff, and tapeout.\n\nCross-Functional Alignment & Coordination\nDrive cross-functional alignment across architecture, RTL design, verification, emulation, DFT, synthesis, physical design, CAD, IP integration, product management, and external partners.\nTrack IP delivery, PDK updates, CAD/EDA flow readiness, tool dependencies, and foundry requirements.\nPartner with Post-Silicon PM and Validation teams to absorb feedback from post silicon bring up, including bug reports and Si issues.\n\nRisk Management & Decision-Making\nIdentify execution risks, lead risk mitigation plans, and drive trade-off decisions across scope, schedule, resources, and quality.\nCommunicate program health, risks, dependencies, and decisions clearly to engineering teams, senior leaders, executives, and external partners.\n\nProcess & Operational Excellence\nEstablish scalable program management practices, operating rhythms, decision forums, documentation standards, and communication mechanisms, lead constant improvement.\n\nBasic Qualifications\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.\n10+ years of experience in ASIC/SoC development or silicon program execution, including 3+ years in technical program management, engineering program management, or technical leadership.\nExperience managing pre-silicon ASIC development flows, including architecture planning, RTL design, functional verification, synthesis, DFT, physical design, timing closure, signoff, and tapeout.\nExperience with advanced process nodes and high-performance ASIC/SoC development.\nStrong understanding of ASIC development milestones from product requirements through final GDS handoff.\nFamiliarity with EDA flows, CAD infrastructure, IP integration, PDK readiness, foundry requirements, and vendor dependency management.\nExperience with pre-silicon validation platforms such as simulation, emulation, FPGA prototyping, or hardware/software co-validation.\nExperience driving complex cross-functional programs with multiple engineering teams, technical dependencies, external vendors, and aggressive schedules.\nPreferred Qualifications\nStrong technical judgment with the ability to manage trade-offs across performance, power, area, cost, schedule, quality, and risk.\nExcellent communication, organizational, leadership, and stakeholder-management skills.\nAbility to influence without authority across global, cross-functional, and cross-cultural teams.\nAbility to operate independently in a fast-paced, ambiguous, high-growth environment.\nExperience with high-speed connectivity, SerDes, PHY, PCIe, CXL, Ethernet, networking, switching, or AI infrastructure silicon.\nSalary range is CAD 195,000 to CAD 240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.\nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.","description_format":"text","description_chars":5172,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Servers & Data Center Hardware"],"lifecycle":[{"event":"open","at":"2026-09-06T11:26:14Z"}],"visa":[{"country":"CA","licensed_sponsor":true,"evidence":"Positions approved through LMIA in 12 months: 1","filings_12m":1,"filings_prev_12m":4,"green_card_filings_12m":null,"median_offered_wage_usd":null,"route":"Global Talent Stream","cap_exempt":false,"checked_at":"2026-10-03T21:10:52+00:00","sources":["ESDC: employers issued a positive LMIA"],"filings_for_role_12m":0}],"liveness":{"score":21,"band":"cold","label":"Long shot","p_open":1,"p_active":0.481,"p_room":0.44,"age_days":110,"expected_fill_days":78,"reasons":["conf:0","stale_co","velocity","win:tail","crowd:brand"],"computed_at":"2026-10-13T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/astera-labs-sr-principal-program-manager-asic-design","json_url":"https://alion.io/job/astera-labs-sr-principal-program-manager-asic-design.json","meta":{"generated_at":"2026-10-13T16:39:00Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"search","counted_by":"address","units_charged":0,"used_today":0,"day_limit":null,"remaining_today":null,"minute_limit":null,"resets_at":"2026-10-14T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":178069},"rest":"https://alion.io/mcp/rest/get_company?id=178069"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fastera-labs-sr-principal-program-manager-asic-design"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fastera-labs-sr-principal-program-manager-asic-design"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fastera-labs-sr-principal-program-manager-asic-design"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/astera-labs-sr-principal-program-manager-asic-design\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fastera-labs-sr-principal-program-manager-asic-design"}]}