{"id":2440198,"url":"https://alion.io/job/astera-labs-teach-lead-physical-design-engineer","title":"Teach Lead Physical Design Engineer","company":{"id":178069,"name":"Astera Labs","domain":"asteralabs.com","url":"https://alion.io/company/astera-labs-2","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"A","score":87,"open_postings":53,"ghost_share":0,"stale_share":0.302,"repost_share":0,"time_to_fill_p50_days":78,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Singapore"],"countries":["SG"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":70000,"max_usd":144000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":36},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Ansys RedHawk","optional":false},{"name":"Cadence Innovus","optional":false},{"name":"NVLink","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false}],"status":"live","first_seen_at":"2026-10-13T08:32:24Z","employer_posted_date":"2026-10-13","last_verified_at":"2026-10-17T22:26:52Z","board_verified":true,"closed_at":null,"days_open":4,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":4},"description":"Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.\nAbout the Role\nWe are seeking a Senior Physical Design Engineer to join our high-performance design team working on next-generation transceiver IPs targeting the TSMC 3nm and advanced technology nodes \nKey Responsibilities\nPerform block-level and top-level physical implementation including floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification for high-speed designs in advanced technology nodes.\n\nCollaborate with RTL and STA teams to ensure clean handoffs and support timing, area, and power convergence.\n\nApply advanced physical design techniques to support multiple voltage and frequency domains, hierarchical design, and physical-aware synthesis.\n\nWork on key physical design areas including:\nEM/IR analysis and power grid optimization\n\nCongestion analysis and mitigation\n\nClock skew optimization and clock quality improvement\n\nRC extraction-aware placement and routing\n\nIntegrate IPs and top-level blocks with attention to physical interfaces, constraints, and timing alignment.\n\nSupport floorplan development and chip partitioning for high-speed transceiver designs.\n\nPerform ECO implementation and assist with tapeout signoff activities.\n\nEnsure DRC, LVS, ANT, CELL, and ERC clean databases using industry-standard physical verification tools.\n\nUse industry-standard tools such as ICC2, Innovus, Voltus, RedHawk, and Calibre for implementation and signoff.\n\nDevelop and maintain automation scripts in Tcl, Python, or Perl to improve physical design flows and productivity.\n\nRequired Qualifications\nBachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or a related field.\n\n5+ years of experience in physical design, preferably with advanced technology nodes.\n\nStrong experience with:\nFloorplanning, placement, CTS, routing, and IR drop mitigation\n\nSignoff checks such as DRC, LVS, ANT, and ERC, along with debugging\n\nTiming closure support in collaboration with STA teams\n\nHands-on use of tools such as Synopsys ICC2, Cadence Innovus, Calibre, and Voltus\n\nExperience integrating high-speed IPs such as SerDes or PHYs into SoC or chiplet-based environments.\n\nExperience working on high-frequency datapath and DSP-related designs.\n\nSolid scripting skills for automation and productivity enhancement.\n\nGood problem-solving skills and the ability to work effectively in cross-functional teams. \n\nWe know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with 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